Leave no stone unturned with AIP+VIP
You are verifying a complex AI or networking chip and found a test failing due to transaction or packet mismatch by scoreboards. As a verification engineer, you would celebrate that you broke the core design intent and found a bug! After hours/days of debugging, all that’s found is a signal on AHB/AXI interface was not connected or a protocol was not followed correctly. Not really a highly effective use of everyone’s time, is it?
Posted in Formal Methodology, Property Verification
