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Iain Singleton

iain-singleton

Iain Singleton is a formal verification specialist in the verification group at Synopsys. Prior to Synopsys, Iain worked in the Advanced Verification Methodologies group at Imagination technologies as a formal engineer tasked with solving tough formal problems across the company. He is based in the UK and joined Synopsys in mid-2016 with a full focus on formal technologies.


Posts by Iain Singleton:

 

21st Century Power SEQers

Power consumption has been an important consideration for IC designs for a while now. Mobile devices today are more powerful than they’ve ever been. I can stream movies, order food, get turn by turn directions and take incredible quality photos and videos using a single device in my pocket… So long as I can make it to the end of the day without the battery running flat. Nobody wants to be in the middle of an important email when the screen suddenly goes black and I’m pretty sure I’m not the only one who’s gone diving into a coffee shop seeking power outlets because of it! These days, we all live with a small amount of power anxiety and 6th sense for hunting down USB sockets and power sources. Combine this with the huge number of servers out there burning power and it’s no surprise that most modern designers are always looking to find that delicate balance of power and performance.

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Posted in Formal Equivalence |

 

Managing Initial State to Head Start Formal Verification

Wouldn’t it be nice to get a head start on some things in life? How great would it be to just be able to walk straight to the front of any queue you find yourself in? For me, I’d like a head start on those long flights from the UK to California. If I could start them somewhere over the Rocky Mountains, then it would be a much more pleasant journey… aside from the mountain waves turbulence! While money, fame or just downright rudeness can potentially get you to the front of a queue, I’m going to have to wait for someone to invent teleportation to cut down that journey time.

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Posted in Formal Methodology, Property Verification |

 

Corner case bugs – Formal got you covered

Imagine the scene. It’s Friday night, and you’ve decided to relax and watch a movie. Given the overwhelming amount of choices, you’ve already spent over an hour watching trailers to choose the movie and you’re finally almost ready to go. All that’s left is the popcorn. You go over to the microwave and get it going. For a little while nothing happens, but then you start to hear the pops, slowly at first but then much more rapidly before beginning to taper off. You then have to ask yourself: When do I stop? This is a big question. Take it out too soon and you’re going to break your teeth on those unpopped kernels. Leave it in too long and you risk burning it. How can you know if its popped long enough?

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Posted in Formal Methodology, Introduction, Property Verification |

 

Divide and Conquer – Formal for Large Designs

As we have discussed in several of the blogs on this forum, successful deployment of Formal verification requires knowing where and how to use it. Building up an arsenal of techniques that can be applied to deal with complexity and knowing how to use them safely is a necessity for every expert Formal engineer.

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Posted in Formal Methodology, Property Verification |

 

Driven to Abstraction

Someday, in the not too distant future, I will be able to fall asleep, play computer games or write a bestselling novel at the wheel (well 2/3 isn’t bad). Until such time however, I have just the one option – concentrate deeply and blast the speakers with my classic rock and punk collection.

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Posted in Property Verification |

 

Goldilocks and the three constraints!

 

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Posted in Formal Methodology, Property Verification |