Posted by System on May 26, 2017
Sean Safarpour has over 15 years of experience in formal verification in both the tool development and application deployment domains. Sean is currently the CAE Director of VC Formal at Synopsys and was previously Sr. Technology Director at Atrenta and Founder/CTO at Vennsa Technologies. Sean received his Ph.D. degree from the University of Toronto.
Dr. Manish Pandey completed his B.Tech, in Computer Science from the Indian Institute of Technology Kharagpur and his PhD in Computer Science from Carnegie Mellon University. He currently leads the R&D teams for formal and static technologies, distributed systems and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry.
Pratik is the R&D Director and product owner for VC Formal, the Formal Verification technology platform at Synopsys. He currently technically leads the diverse R&D team for formal technologies at Synopsys. He has 20+ years of experience in formal verification tool development. He was a technical lead with Incisive Formal Verifier (IFV), and Hardware Equivalence Checker (HECK) at Cadence. He has been granted 2 patents for his innovations in formal technologies.
Ravindra Aneja is a Senior Staff Program Manager at Synopsys, responsible for formal verification solutions. He has 24 years of experience in functional verification domain which includes simulation, hardware acceleration, emulation, assertion based formal verification and clock domain crossing verification. Prior to Synopsys, he held technical marketing and application engineering positions at Atrenta, Mentor Graphics, 0-In Design Automation and IKOS Systems.
Xiaolin Chen has been working at Synopsys for 15 years on application of formal technology in verification, working with customers to explore opportunities where formal technology can be best suited to solve verification problems. She provides guidance, training, and assistance to customers as well as Synopsys field and design teams in developing formal verification environment.
Anders is a senior corporate applications engineer in Synopsys’ Verification Group working on formal methodology and features on the VC Formal tool. He has 20 years’ experience of assertion based verification and formal property verification both from EDA and as a verification engineer.
Abhishek Muchandikar is a Staff Corporate Applications Engineer in Synopsys’ Verification Group. He has over 11 years of experience in the verification domain having worked upon formal and simulation based methodologies. He has previously worked on software telecom protocols. He holds a Master’s Degree in Microelectronics from Victoria University, Melbourne, Australia
Iain Singleton is a formal verification specialist in the verification group at Synopsys. Prior to Synopsys, Iain worked in the Advanced Verification Methodologies group at Imagination technologies as a formal engineer tasked with solving tough formal problems across the company. He is based in the UK and joined Synopsys in mid-2016 with a full focus on formal technologies.
Kiran Vittal is a product marketing director at Synopsys, with 25 years of experience in EDA and semiconductor design. Prior to joining Synopsys, Kiran held product marketing, field applications and engineering positions at Atrenta, ViewLogic, and Mentor Graphics. He holds a MBA from Santa Clara University and a Bachelors in Electronics Engineering from India.