InFormal Chat

Archive for 2019

 

SNUG Silicon Valley 2019: Formal Verification Update

Like last year, we had number of papers presented at our annual SNUG event last month. We had a track dedicated to formal verification, which had 3 papers from customers and 1 tutorial from Synopsys. In a parallel track on AI/ML, we had an additional tutorial from Synopsys where we discussed how formal is best suited to make use of machine learning techniques.

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Leave no stone unturned with AIP+VIP

You are verifying a complex AI or networking chip and found a test failing due to transaction or packet mismatch by scoreboards. As a verification engineer, you would celebrate that you broke the core design intent and found a bug! After hours/days of debugging, all that’s found is a signal on AHB/AXI interface was not connected or a protocol was not followed correctly. Not really a highly effective use of everyone’s time, is it?

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Posted in Formal Methodology, Property Verification | Comments Off on Leave no stone unturned with AIP+VIP