InFormal Chat

Archive for 2019

 

Leave no stone unturned with AIP+VIP

You are verifying a complex AI or networking chip and found a test failing due to transaction or packet mismatch by scoreboards. As a verification engineer, you would celebrate that you broke the core design intent and found a bug! After hours/days of debugging, all that’s found is a signal on AHB/AXI interface was not […]

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Posted in Formal Methodology, Property Verification | Comments Off on Leave no stone unturned with AIP+VIP