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InFormal Chat
I’m too lazy to read…show me a video
Posted by Sean Safarpour on July 8th, 2019
I can’t remember when I last opened a technical manual or document to looked up how to do something. Maybe it was when I bought a 56K modem in 1999 to connect to the World Wide Web.
SNUG Silicon Valley 2019: Formal Verification Update
Posted by Ravindra Aneja on April 30th, 2019
Like last year, we had number of papers presented at our annual SNUG event last month. We had a track dedicated to formal verification, which had 3 papers from customers and 1 tutorial from Synopsys. In a parallel track on AI/ML, we had an additional tutorial from Synopsys where we discussed how formal is best suited to make use of machine learning techniques.
Leave no stone unturned with AIP+VIP
Posted by Nitin Mhaske on January 29th, 2019
You are verifying a complex AI or networking chip and found a test failing due to transaction or packet mismatch by scoreboards. As a verification engineer, you would celebrate that you broke the core design intent and found a bug! After hours/days of debugging, all that’s found is a signal on AHB/AXI interface was not connected or a protocol was not followed correctly. Not really a highly effective use of everyone’s time, is it?
21st Century Power SEQers
Posted by Iain Singleton on September 24th, 2018
Power consumption has been an important consideration for IC designs for a while now. Mobile devices today are more powerful than they’ve ever been. I can stream movies, order food, get turn by turn directions and take incredible quality photos and videos using a single device in my pocket… So long as I can make it to the end of the day without the battery running flat. Nobody wants to be in the middle of an important email when the screen suddenly goes black and I’m pretty sure I’m not the only one who’s gone diving into a coffee shop seeking power outlets because of it! These days, we all live with a small amount of power anxiety and 6th sense for hunting down USB sockets and power sources. Combine this with the huge number of servers out there burning power and it’s no surprise that most modern designers are always looking to find that delicate balance of power and performance.
You don’t have to take my word for it: Machine Learning has a place in Formal Verification
Posted by Sean Safarpour on August 29th, 2018
Just over a year ago I wrote a blog about the impact of machine learning (ML) algorithms to boost Formal Verification performance . The data for that blog was firsthand experience on a set of complex benchmarks. The data was amazing and quite convincing, but when I wrote that blog the reader needed to “trust” me as the data could not be shared publicly.
World Cup Champion and Formal Verification at DAC 2018
Posted by Xiaolin Chen on July 16th, 2018
What an exciting World Cup 2018! The whole world was glued to the television. People were rooting for their favorite teams and in awe of the skills demonstrated by many players. The spirit of World Cup reminds of this year’s DAC event, just a few weeks ago.
Managing Initial State to Head Start Formal Verification
Posted by Iain Singleton on June 20th, 2018
Wouldn’t it be nice to get a head start on some things in life? How great would it be to just be able to walk straight to the front of any queue you find yourself in? For me, I’d like a head start on those long flights from the UK to California. If I could start them somewhere over the Rocky Mountains, then it would be a much more pleasant journey… aside from the mountain waves turbulence! While money, fame or just downright rudeness can potentially get you to the front of a queue, I’m going to have to wait for someone to invent teleportation to cut down that journey time.
Artificial Intelligence, let us get the math right first!
Posted by Ravindra Aneja on May 22nd, 2018
Artificial intelligence is a hot topic these days and therefore doesn’t require a repeat of the current and future potential uses for AI. For most people it means technology advancements on the software side but If you ask people who are very close to this technology domain, building your own optimized hardware chips is where significant part of the competitive edge lies.
Formal Verification Showcase – DVCon 2018 and SNUG Silicon Valley 2018
Posted by Ravindra Aneja on April 12th, 2018
It should not be news to the readers that Formal verification is an integral part of verification flows for the majority of leading edge SoC design and IP companies. A good indicator for this is the amount of papers, posters and tutorials presented at recent industry events/conferences in Silicon Valley.
Don’t have a Meltdown over a Spectre in your SoC
Posted by Anders Nordstrom on March 20th, 2018
You may be concerned about the widely published Spectre and Meltdown vulnerabilities affecting most processors, and if your phone and computer are OK. Or more importantly, if you are designing or verifying SoCs, do you have a specter in your design? Let’s first look at what these two vulnerabilities are and how they are affecting your system.
