From Silicon To Software

Archive for the 'Verification' Category

 

How High-Speed Functional Interfaces Enable Fast, In-Field Silicon Testing

Explore the silicon testing methods that replace existing I/O with functional interfaces which reduce testing time and enable product lifecycle management.

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Posted in Internet of Things, IP, Prototyping, Verification

 

Achieving Faster Turnaround Time on Engineering Change Orders

Explore the Functional ECO (engineering change order) process and learn how to accelerate the SoC design flow and reduce iterations with first-time-right ECOs.

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Posted in Product Spotlight, Verification

 

Achieving Greater Safety for Tomorrow’s Autonomous Vehicles

Autonomous vehicle safety and cybersecurity starts with automotive SoC design, protecting connected vehicles against data tampering and physical attacks.

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Posted in Application Security, Automotive, Verification

 

AI: The Next Chapter in the Evolution of Verification

We look at how AI and machine learning boost SoC verification, enhancing both static and formal verification and increasing chip simulation performance.

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Posted in Artificial Intelligence, Product Spotlight, Verification

 

How Can SmartNICs Move Your Data Center Forward?

Learn how programmable SmartNICs enable homogeneous data center networking and storage architectures while taking the load off of primary compute resources.

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Posted in 3D-ICs, Cloud, EDA, HPC, IP, Verification

 

Synopsys Cloud SaaS Instances: Faster Time-to-Market for Higher Quality Chips

See how cloud-based EDA tools and ready-to-use chip design flows accelerate the SoC design & verification process, thanks to Saas Instances on Synopsys Cloud.

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Posted in Cloud, EDA, Product Spotlight, Verification

 

Get a Head Start in Formal Verification with Synopsys Formal Consulting Services

Explore the formal verification process and see how our team can ramp up SoC design productivity with verification audits, trainings, and project consulting.

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Posted in Verification

 

How Are Fault Simulation Technologies Keeping Pace with Growing Chip Complexity?

Learn how fault simulation techniques are evolving to meet growing chip design complexity, including unified functional safety verification platforms.

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Posted in Verification

 

Collaborating to Ensure that Software Just Works Across Arm-Based Hardware

Explore Arm’s SystemReady program, and learn how we’re simplifying hardware/software compliance through pre-silicon testing for Base System Architecture (BSA).

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Posted in IP, Verification

 

Integration Challenges for Multi-Billion Gate ASICs: Part 3 – Static Linting

Explore the challenges of static linting of code and learn how static linting tools speed up the ASIC development process for faster chip design signoff.

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Posted in Verification