From Silicon To Software

Archive for the 'Verification' Category

 

What’s Driving the World’s First Analog and Mixed-Signal Emulation Technology?

Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA’s POSH and ERI programs, emulates analog designs.

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Posted in Aerospace and Government, Application Security, Security, Verification

 

How to Speed Up Simulation Coverage Closure with Formal Verification Tools

We explore how formal verification tools synergize with simulation technology to accelerate coverage closure in the SoC design and verification process.

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Posted in Product Spotlight, Verification

 

Why Sacrifice QoRs? Optimizing Design Signoff and Achieving Accurate Functional ECOs the Smarter Way

Learn how formal equivalence checking and functional ECO tools accelerate SoC verification and streamline chip design signoff with machine learning.

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Posted in Product Spotlight, Verification

 

Don’t Let the Bugs Bite: Reducing Design Reworks and Errors with Advanced Linting (Part 1)

Learn how advanced code linting accelerates the RTL & SoC design flow, testing for and verifying functional chip design issues before testbenches are available.

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Posted in Verification

 

Standing the Test of Time: How Advanced Protocol Verification Creates Bulletproof SoC Designs

We explore the role of advanced protocol verification for interface standards in the SoC design flow, as PCIe 6.0, HBM3, and 800G Ethernet continue to evolve.

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Posted in IP, Verification

 

Get the Most Out of Your Next-Generation PCIe 6.0.1 Design

Learn about the new PCIe 6.0.1 specification and explore the role of PCI-SIG certified controller & verification IP for end-to-end protocol verification.

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Posted in Cloud, Internet of Things, IP, Verification

 

Don’t Let Faults in the Field Spoil Safety-Critical Designs

We explore how integrating functional verification and fault simulation techniques helps protect safety-critical chip designs from faults in the field.

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Posted in Verification

 

AI-Driven Debug Automation Enables 4x Acceleration of Regression Root-Cause Analysis

We explain how AI-enabled debugging automation accelerates chip verification by reducing regression turnaround time during root-cause analysis (RCA).

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Posted in Verification

 

Customer Spotlight: Neuchips Tapes Out Groundbreaking AI Accelerator

See how virtual prototyping, chip verification, and EDA tools helped Neuchips design an AI accelerator chip for the deep learning recommendation model (DLRM).

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Posted in Artificial Intelligence, Customer Spotlight, IP, Verification

 

ST Crushes Design Bugs with Power-Aware CDC and RDC Verification

STMicroelectronics’ power-aware clock domain crossing (CDC) & reset domain crossing (RDC) verification methodology resolves chip design errors at the RTL stage.

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Posted in Customer Spotlight, Verification