New Horizons for Chip Design

Archive for the 'Verification' Category


From Silicon Design to End of Life—Mitigate Memory Failures to Boost Reliability

See how memory design techniques boost reliability throughout the silicon lifecycle and learn the difference between safety & reliability in electronic design.

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Posted in 5G, Automotive, HPC, Internet of Things, Multi-Die Systems, Verification


How Cloud IC Verification Reduced DRC Runtimes by 65%

Chip designers are rapidly migrating to EDA tools in the cloud; learn why and explore trends in chip design tools from our panel at SNUG Silicon Valley 2023.

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Posted in Cloud, IP, Verification


How to Shift Left on Low-Power Design Verification, Early and Quickly

Learn how low power chip design verification can be shifted left in the SoC design flow, allowing chip designers to clean up UPF issues before RTL is ready.

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Posted in Product Spotlight, Verification


Synopsys Acquires Silicon Frontline Technology

See how our acquisition of Silicon Frontline Technology enhances IC design tools for power semiconductor devices through power device design & ESD verification.

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Posted in Inside Synopsys, Power, Verification


Imparé Imparts Its Insights on Verification in the Cloud

Learn how Impare uses cloud-based chip design verification tools and explore the time, scalability and collaboration advantages of EDA tools in the cloud.

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Posted in Cloud, Customer Spotlight, Verification


The Wonders of Machine Learning: Tackling Lint Debug Quickly with Root-Cause Analysis (Part 3)

Learn how advanced linting tools powered by machine learning accelerate the SoC design flow and chip design signoff for automotive and emerging applications.

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Posted in EDA, Machine Learning, Verification


How to Achieve Faster Signoff of Billion-Gate, Low-Power SoCs

Learn how to accelerate the low-power SoC design verification flow with machine learning for faster, more comprehensive static analysis and functional verification.

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Posted in Machine Learning, Product Spotlight, Verification


How AI Drives Faster Chip Verification Coverage and Debug for First-Time-Right Silicon

Learn how AI-enabled EDA tools accelerate the SoC design verification flow and chip debug cycle for first-time-right chip designs and faster time-to-market.

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Posted in Artificial Intelligence, Verification


Execute Your Hardware Verification Campaign in the Cloud – a Verification Engineer’s Perspective

We explain how cloud-based hardware IP verification saves valuable time in the hardware design flow by automating SoC simulation and reducing time to debug.

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Posted in Cloud, Verification


Your New “Superpower”: See Through “Hand-Off Walls” for Implementation PPA Insights on Early-Stage RTL

Learn how to optimize the RTL design flow with real-time PPA analysis and chip design insights from physically aware RTL analysis and automated debug tools.

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Posted in Product Spotlight, Verification