From Silicon To Software

Archive for the 'Verification' Category

 

Why Wait Days for Results? The Next Frontier for Power Verification

Learn why SoC emulation is the next frontier for power system optimization, helping chip designers shift power verification left in the SoC design flow.

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Posted in Power, Prototyping, Verification

 

What’s Driving the Demand for 200G, 400G, and 800G Ethernet?

Hyperscale data centers are driving demand for high-bandwidth Ethernet protocols at speeds up to 800G to support HPC, AI, video streaming, and cloud computing.

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Posted in Artificial Intelligence, HPC, IP, Verification

 

Take the Guesswork Out of Designing Your New Product Architecture

We explain how virtual prototyping eliminates ASIC design bugs before RTL, and how chip architecture design modeling correlates key performance attributes.

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Posted in Artificial Intelligence, Prototyping, Verification

 

Running a Trillion-Cycle Application Workload with Fast SoC Emulation

Explore the impact of high-performance SoC emulation on chip design & learn how full-visibility debugging gives designers a jump on SoC verification.

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Posted in 5G, Artificial Intelligence, Automotive, HPC, Verification

 

Empowered By Real-World Software to Find Power Bugs

We explain how to find dynamic power & leakage power bugs during SoC verification, using pre-silicon emulation for full-stack system-level power analysis.

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Posted in Artificial Intelligence, Automotive, HPC, Power, Verification

 

The Quest for the Most Advanced Networking SoC: Achieving Breakthrough Verification Efficiency with Cloud-Based Emulation

Learn how cloud-based SoC design and functional verification systems such as ZeBu Cloud accelerate networking SoC readiness across both hardware & software.

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Posted in Cloud, EDA, Verification

 

Synopsys Makes Headlines with PrimeSim Continuum, an Innovative Circuit Simulation Solution

Our new IC design tool, PrimeSim Continuum, enables the next generation of hyper-convergent IC designs. Learn more from eeNews, Electronic Design & EE Times.

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Posted in 3D-ICs, EDA, Machine Learning, Prototyping, Verification

 

Find Bugs Earlier Via On-the-Fly Code Checking for Productive Chip Design and Verification

Learn how correct-by-construction coding enables a more productive chip design process, as new code review tools address bugs early in the design process.

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Posted in Verification

 

Advanced Nodes Drive Demand for Advanced Library Characterization and Validation Solutions

Introducing PrimeLib, an SoC design tool that maps the latest chip technologies & enables correct-by-construction design for SoCs at advanced process nodes.

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Posted in 3D-ICs, EDA, Prototyping, Verification

 

PrimeSim Continuum Meets the Challenge of Hyper-Convergent ICs with Faster SPICE Engines and a More Unified Simulation Workflow

Learn how PrimeSim Continuum, our new IC design solution, delivers the IC verification tools & SPICE simulation speed needed for modern hyper-convergent ICs.

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Posted in 3D-ICs, EDA, Machine Learning, Prototyping, Verification