From Silicon To Software

Archive for the 'Verification' Category

 

Find Bugs Earlier Via On-the-Fly Code Checking for Productive Chip Design and Verification

Learn how correct-by-construction coding enables a more productive chip design process, as new code review tools address bugs early in the design process.

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Posted in Verification

 

Advanced Nodes Drive Demand for Advanced Library Characterization and Validation Solutions

Introducing PrimeLib, an SoC design tool that maps the latest chip technologies & enables correct-by-construction design for SoCs at advanced process nodes.

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Posted in 3D-ICs, EDA, Prototyping, Verification

 

PrimeSim Continuum Meets the Challenge of Hyper-Convergent ICs with Faster SPICE Engines and a More Unified Simulation Workflow

Learn how PrimeSim Continuum, our new IC design solution, delivers the IC verification tools & SPICE simulation speed needed for modern hyper-convergent ICs.

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Posted in 3D-ICs, EDA, Machine Learning, Prototyping, Verification

 

Scaling FPGA-Based Prototyping to Meet Verification Demands of Complex SoCs

Explore the history of FPGA prototyping in the SoC design/verification process and learn about HAPS-100, a new prototyping system for complex AI & HPC SoCs.

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Posted in 3D-ICs, 5G, Artificial Intelligence, EDA, HPC, Prototyping, Verification

 

Synopsys and IBM Research: Driving Real Progress in Large-Scale AI Silicon and Implementing a Hybrid Cloud Model for Chip Design

Hybrid Cloud architecture enables innovation in AI chip design; learn how our partnership with IBM combines the best in EDA & HPC to improve AI performance.

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Posted in Artificial Intelligence, EDA, Verification

 

Get Actionable Power Verification Results in Hours on Billion-Gate Designs

Power analysis is key to the SoC design process; learn how emulation solutions deliver actionable power verification results in hours to help meet PPA targets.

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Posted in 5G, Artificial Intelligence, Power, Verification

 

Why Datapath Validation Is Important—and How HECTOR Technology Can Help

With DVCon 2021 on the horizon we share a primer on our datapath verification technology HECTOR, exploring its impact on machine learning & AI chip design.

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Posted in Artificial Intelligence, Machine Learning, Verification

 

2020 Recap: “Smart Everything” Year in Review

We cap off 2020 with a look at this year’s Smart Everything developments, including AI advancements, new EDA tools, 5G’s global rollout, and security in design.

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Posted in 5G, Aerospace and Defense, Application Security, Artificial Intelligence, Automotive, EDA, HPC, Inside Synopsys, Internet of Things, Optical Design, Prototyping, Security, Verification

 

Q&A with Synopsys Scientist Lisa McIlwain: Advancing Women in STEM

We sit down with Synopsys Scientist Lisa McIlwain to discuss her career path, circuit design verification, & the challenges of advancing women in STEM careers.

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Posted in EDA, Verification

 

FPGA Prototyping Brings More Performance, Scalability to SoC Hardware and Software Development (Part 3)

FPGA prototyping uses the high-capacity field-programmable gate arrays prototyping process; learn how FPGA programming increases performance and scalability in the SoC design cycle.

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Posted in Prototyping, Verification