Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA’s POSH and ERI programs, emulates analog designs.
Posted in Aerospace and Government, Application Security, Security, Verification
We explore how formal verification tools synergize with simulation technology to accelerate coverage closure in the SoC design and verification process.
Posted in Product Spotlight, Verification
Learn how formal equivalence checking and functional ECO tools accelerate SoC verification and streamline chip design signoff with machine learning.
Posted in Product Spotlight, Verification
Learn how advanced code linting accelerates the RTL & SoC design flow, testing for and verifying functional chip design issues before testbenches are available.
Posted in Verification
We explore the role of advanced protocol verification for interface standards in the SoC design flow, as PCIe 6.0, HBM3, and 800G Ethernet continue to evolve.
Posted in IP, Verification
Learn about the new PCIe 6.0.1 specification and explore the role of PCI-SIG certified controller & verification IP for end-to-end protocol verification.
Posted in Cloud, Internet of Things, IP, Verification
We explore how integrating functional verification and fault simulation techniques helps protect safety-critical chip designs from faults in the field.
Posted in Verification
We explain how AI-enabled debugging automation accelerates chip verification by reducing regression turnaround time during root-cause analysis (RCA).
Posted in Verification
See how virtual prototyping, chip verification, and EDA tools helped Neuchips design an AI accelerator chip for the deep learning recommendation model (DLRM).
Posted in Artificial Intelligence, Customer Spotlight, IP, Verification
STMicroelectronics’ power-aware clock domain crossing (CDC) & reset domain crossing (RDC) verification methodology resolves chip design errors at the RTL stage.
Posted in Customer Spotlight, Verification
