Learn how low-power design techniques such as clock gating, multi voltage domains, and register retention enable efficient IoT SoCs and IoT edge devices.
Effective SoC verification requires realistic software workloads during full chip power signoff; explore advantages of SoC emulation such as RTL power analysis.
We explain how advanced power management techniques including Unified Power Format (UPF) expand low power design techniques and enhance IC design efficiency.
Fall 2021 silicon design events are almost here! Join us for ARC Processor Virtual Summit, Verification Day 2021, and the Digital Design Technology Symposium.
Learn why SoC emulation is the next frontier for power system optimization, helping chip designers shift power verification left in the SoC design flow.
We explain how to find dynamic power & leakage power bugs during SoC verification, using pre-silicon emulation for full-stack system-level power analysis.
Q&A with Dr. Renu Mehra of Synopsys Silicon Realization Group: Pioneering Automated Power Management Technologies for Chip Design
We discuss low power design with Dr. Renu Mehra, R&D group director in our Digital Design Group, along with her career in STEM & the future of RTL synthesis.
Power analysis is key to the SoC design process; learn how emulation solutions deliver actionable power verification results in hours to help meet PPA targets.
We explain how AI chip designers can address SoC glitch power & reduce hardware power consumption early in the design cycle by leveraging chip design tools.
We discuss chip design predictions for 2021, including Artificial Intelligence & Internet of Things’ unique power management challenges between HPC & edge SoCs.
Posted in Power