How the Electronics Industry Can Shape a More Sustainable, Energy-Efficient World
We explore hyperscale datacenters & internet traffic’s impact on climate change and discuss how energy-efficient system design shapes a sustainable future.
We explore hyperscale datacenters & internet traffic’s impact on climate change and discuss how energy-efficient system design shapes a sustainable future.
Learn how low-power design techniques such as clock gating, multi voltage domains, and register retention enable efficient IoT SoCs and IoT edge devices.
Posted in Internet of Things, Power
Effective SoC verification requires realistic software workloads during full chip power signoff; explore advantages of SoC emulation such as RTL power analysis.
Posted in Power, Verification
We explain how advanced power management techniques including Unified Power Format (UPF) expand low power design techniques and enhance IC design efficiency.
Posted in Power, Verification
Fall 2021 silicon design events are almost here! Join us for ARC Processor Virtual Summit, Verification Day 2021, and the Digital Design Technology Symposium.
Posted in Artificial Intelligence, Automotive, EDA, HPC, Inside Synopsys, Internet of Things, IP, Machine Learning, Multi-Die Systems, Power, Verification
Learn why SoC emulation is the next frontier for power system optimization, helping chip designers shift power verification left in the SoC design flow.
Posted in Power, Prototyping, Verification
We explain how to find dynamic power & leakage power bugs during SoC verification, using pre-silicon emulation for full-stack system-level power analysis.
Posted in Artificial Intelligence, Automotive, HPC, Power, Verification
We discuss low power design with Dr. Renu Mehra, R&D group director in our Digital Design Group, along with her career in STEM & the future of RTL synthesis.
Posted in Inside Synopsys, Power
Power analysis is key to the SoC design process; learn how emulation solutions deliver actionable power verification results in hours to help meet PPA targets.
Posted in 5G, Artificial Intelligence, Power, Verification
We explain how AI chip designers can address SoC glitch power & reduce hardware power consumption early in the design cycle by leveraging chip design tools.
Posted in Artificial Intelligence, Power