New Horizons for Chip Design

Archive for the 'Power' Category

 

Synopsys Acquires Silicon Frontline Technology

See how our acquisition of Silicon Frontline Technology enhances IC design tools for power semiconductor devices through power device design & ESD verification.

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Posted in Inside Synopsys, Power, Verification

 

Celebrating Earth Day: Creating a Smart Future

We celebrate Earth Day 2023 by exploring how an environmentally responsible chip supply chain and SoC development process can reduce global energy consumption.

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Posted in Inside Synopsys, Power

 

How the Electronics Industry Can Shape a More Sustainable, Energy-Efficient World

We explore hyperscale datacenters & internet traffic’s impact on climate change and discuss how energy-efficient system design shapes a sustainable future.

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Posted in EDA, IP, Power

 

Accelerating IoT Designs: Designing for Low Power in the Era of Smart Everything

Learn how low-power design techniques such as clock gating, multi voltage domains, and register retention enable efficient IoT SoCs and IoT edge devices.

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Posted in Internet of Things, Power

 

Why You MUST Run Realistic Software for Full Chip Power Signoff

Effective SoC verification requires realistic software workloads during full chip power signoff; explore advantages of SoC emulation such as RTL power analysis.

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Posted in Power, Verification

 

Unified Power Format (UPF) and Beyond: How to Expand Low-Power Signoff

We explain how advanced power management techniques including Unified Power Format (UPF) expand low power design techniques and enhance IC design efficiency.

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Posted in Power, Verification

 

Sharpen Your Silicon Design Expertise at Synopsys Events this Fall

Fall 2021 silicon design events are almost here! Join us for ARC Processor Virtual Summit, Verification Day 2021, and the Digital Design Technology Symposium.

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Posted in Artificial Intelligence, Automotive, EDA, HPC, Inside Synopsys, Internet of Things, IP, Machine Learning, Multi-Die Systems, Power, Verification

 

Why Wait Days for Results? The Next Frontier for Power Verification

Learn why SoC emulation is the next frontier for power system optimization, helping chip designers shift power verification left in the SoC design flow.

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Posted in Power, Prototyping, Verification

 

Empowered By Real-World Software to Find Power Bugs

We explain how to find dynamic power & leakage power bugs during SoC verification, using pre-silicon emulation for full-stack system-level power analysis.

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Posted in Artificial Intelligence, Automotive, HPC, Power, Verification

 

Q&A with Dr. Renu Mehra of Synopsys Silicon Realization Group: Pioneering Automated Power Management Technologies for Chip Design

We discuss low power design with Dr. Renu Mehra, R&D group director in our Digital Design Group, along with her career in STEM & the future of RTL synthesis.

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Posted in Inside Synopsys, Power