See how memory design techniques boost reliability throughout the silicon lifecycle and learn the difference between safety & reliability in electronic design.
Posted in 5G, Automotive, HPC, Internet of Things, Multi-Die Systems, Verification
Multi-die systems are the future of the semiconductor industry; explore the role of 3D packaging and chiplet standards including UCIe in our trends report.
Posted in Multi-Die Systems
Explore the design challenges of integrated thermal management solutions for multi-die systems, and how AI-enabled EDA tools help, as covered at SNUG 2023.
Posted in Multi-Die Systems
Explore how semiconductor companies integrate chiplets and heterogeneous dies in multi-die systems to power everything from autonomous driving to generative AI.
Posted in Multi-Die Systems
We celebrate the 76th anniversary of the transistor by explaining how transistors work, how they’re used, and what’s next in GAA transistors and multi-die systems.
Posted in Multi-Die Systems
Learn how we’re enhancing 3D IC packaging with PSMC and accelerating AI inference by enabling wafer-on-wafer (WoW) and chip-on-wafer (CoW) stacking for DRAM.
Posted in Artificial Intelligence, Multi-Die Systems
From AI chip design tools to multi-die systems, explore the top trends shared by CEO Aart de Geus during his keynote speech at SNUG Silicon Valley 2023.
Posted in Artificial Intelligence, EDA, Inside Synopsys, IP, Multi-Die Systems
We unpack the Universal Chiplet Interconnect Express (UCIe) standard and explain its benefits for multi-die systems and testing/verification requirements.
Posted in IP, Multi-Die Systems
Learn how (and why) the semiconductor industry is moving towards chiplet-enabled multi-die systems in our research piece in MIT’s Technology Review Insights.
Posted in Multi-Die Systems
We’re advancing development of chiplet-based multi-die systems with a successful UCIe PHY IP tape-out on TSMC’s N3E semiconductor manufacturing process.
Posted in IP, Multi-Die Systems
