New Horizons for Chip Design

Archive for the 'Multi-Die Systems' Category

 

From Silicon Design to End of Life—Mitigate Memory Failures to Boost Reliability

See how memory design techniques boost reliability throughout the silicon lifecycle and learn the difference between safety & reliability in electronic design.

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Posted in 5G, Automotive, HPC, Internet of Things, Multi-Die Systems, Verification

 

New Synopsys Report Highlights Key Industry Insights on the Impact of Multi-Die Systems

Multi-die systems are the future of the semiconductor industry; explore the role of 3D packaging and chiplet standards including UCIe in our trends report.

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Posted in Multi-Die Systems

 

Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?

Explore the design challenges of integrated thermal management solutions for multi-die systems, and how AI-enabled EDA tools help, as covered at SNUG 2023.

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Posted in Multi-Die Systems

 

­­­­­How Multi-Die Systems Create New Business Opportunities for Semiconductor Companies

Explore how semiconductor companies integrate chiplets and heterogeneous dies in multi-die systems to power everything from autonomous driving to generative AI.

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Posted in Multi-Die Systems

 

76 Years of the Transistor: Then, Now, and What’s to Come

We celebrate the 76th anniversary of the transistor by explaining how transistors work, how they’re used, and what’s next in GAA transistors and multi-die systems.

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Posted in Multi-Die Systems

 

Synopsys and Powerchip Deliver New Advanced 3DIC Packaging Solution for AI Applications

Learn how we’re enhancing 3D IC packaging with PSMC and accelerating AI inference by enabling wafer-on-wafer (WoW) and chip-on-wafer (CoW) stacking for DRAM.

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Posted in Artificial Intelligence, Multi-Die Systems

 

SNUG Silicon Valley 2023: Catalyzing the Future for Our Smart Everything World

From AI chip design tools to multi-die systems, explore the top trends shared by CEO Aart de Geus during his keynote speech at SNUG Silicon Valley 2023.

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Posted in Artificial Intelligence, EDA, Inside Synopsys, IP, Multi-Die Systems

 

Meeting Requirements for UCIe-Based Multi-Die Systems Success

We unpack the Universal Chiplet Interconnect Express (UCIe) standard and explain its benefits for multi-die systems and testing/verification requirements.

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Posted in IP, Multi-Die Systems

 

An Industry-Wide Look at the Move Toward Multi-Die Systems

Learn how (and why) the semiconductor industry is moving towards chiplet-enabled multi-die systems in our research piece in MIT’s Technology Review Insights.

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Posted in Multi-Die Systems

 

Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process

We’re advancing development of chiplet-based multi-die systems with a successful UCIe PHY IP tape-out on TSMC’s N3E semiconductor manufacturing process.

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Posted in IP, Multi-Die Systems