New Horizons for Chip Design

Archive for the 'IP' Category


How Cloud IC Verification Reduced DRC Runtimes by 65%

Chip designers are rapidly migrating to EDA tools in the cloud; learn why and explore trends in chip design tools from our panel at SNUG Silicon Valley 2023.

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Posted in Cloud, IP, Verification


How the CXL Standard Improves Latency in High-Performance Computing

Explore the Compute Express Link (CXL) protocol and learn how it uses memory pooling to reduce latency for high-performing computing (HPC) systems via PCIe.

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Posted in HPC, IP


UFS 4.0 Explained: How the Latest Flash Storage Standard Propels Our 5G World

We explain the UFS 4.0 specification for flash storage and explore how data transfer rates up to 5800 MBps enhance smartphones, vehicles, AR/VR, and beyond.

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Posted in 5G, IP, Security


SNUG Silicon Valley 2023: Catalyzing the Future for Our Smart Everything World

From AI chip design tools to multi-die systems, explore the top trends shared by CEO Aart de Geus during his keynote speech at SNUG Silicon Valley 2023.

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Posted in Artificial Intelligence, EDA, Inside Synopsys, IP, Multi-Die Systems


Meeting Requirements for UCIe-Based Multi-Die Systems Success

We unpack the Universal Chiplet Interconnect Express (UCIe) standard and explain its benefits for multi-die systems and testing/verification requirements.

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Posted in IP, Multi-Die Systems


How the MACsec Protocol Keeps Ethernet Networks Secure

We explain how the MACsec protocol works as one of the fundamentals of network security, ensuring Ethernet interface security for automotive, HPC and beyond.

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Posted in 5G, Automotive, Cloud, HPC, IP, Security


Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks

Learn how to design security into high-bandwidth DDR memory interfaces and protect DRAM devices & data from memory-scraping attacks like Rowhammer & RAMbleed.

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Posted in Internet of Things, IP, Security


Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process

We’re advancing development of chiplet-based multi-die systems with a successful UCIe PHY IP tape-out on TSMC’s N3E semiconductor manufacturing process.

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Posted in IP, Multi-Die Systems


Tech Talks and More on Tap for Synopsys Users at SNUG Silicon Valley 2023

From chiplet-powered multi-die systems to EDA workflows in the cloud, stay on top of the electronics industry’s latest trends at SNUG Silicon Valley 2023!

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Posted in Artificial Intelligence, Cloud, EDA, IP, Multi-Die Systems


Reduce Integration Risks for High-Speed Applications with PCIe 5.0-Compliant Synopsys IP

Our PCIe 5.0 IP solutions, including digital controllers and PHYs, have passed PCI-SIG 5.0 compliance testing, becoming the first on the 5.0 integrators list.

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Posted in IP