From Silicon To Software

Archive for the 'IP' Category

 

HBM3 Will Feed the Growing Need for Speed

High-Bandwidth Memory (HBM) interfaces prevent bottlenecks in online games, AI applications, and more; we explore design challenges and IP solutions for HBM3.

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Posted in IP

 

7 Tips for Benchmarking Embedded Processor IP for AI SoCs

Learn how to benchmark AI processors and select the optimal embedded processor IP and neural network accelerator for each AI application’s unique requirements.

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Posted in Artificial Intelligence, IP

 

Q&A with Priyanka Joshi, Women in Semiconductor Hardware (WISH) Conference Paper Presenter

We sat down with intern Priyanka Joshi to discuss low-power, mixed-signal DDR design ahead of the 2021 Women in Semiconductor Hardware (WISH) conference.

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Posted in Inside Synopsys, IP

 

Sharpen Your Silicon Design Expertise at Synopsys Events this Fall

Fall 2021 silicon design events are almost here! Join us for ARC Processor Virtual Summit, Verification Day 2021, and the Digital Design Technology Symposium.

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Posted in 3D-ICs, Artificial Intelligence, Automotive, EDA, HPC, Inside Synopsys, Internet of Things, IP, Machine Learning, Power, Verification

 

How IP-Enabled SoC Design Is Driving Growth Across All Aspects of Dynamic and Diverse HPC Requirements

Explore how silicon-proven IP for HPC SoC design is driving growth across HPC applications such as network infrastructure, machine learning & AI accelerators.

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Posted in HPC, IP

 

What Is a Multi-Die Design—and What’s Driving Its Growing Popularity?

Explore the growing popularity of multi-die chip designs and learn how a system-level view helps chip designers reach aggressive PPA targets for data centers.

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Posted in 3D-ICs, 5G, Artificial Intelligence, HPC, IP

 

Why Processor Workloads Are Changing as Moore’s Law Slows

Explore how processor workloads are changing as Moore’s Law slows, driving new processor architectures that meet the performance requirements of modern SoCs.

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Posted in 5G, Artificial Intelligence, IP

 

What’s Driving the Demand for 200G, 400G, and 800G Ethernet?

Hyperscale data centers are driving demand for high-bandwidth Ethernet protocols at speeds up to 800G to support HPC, AI, video streaming, and cloud computing.

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Posted in Artificial Intelligence, HPC, IP, Verification

 

Customer Spotlight: Aaroh Labs Delivers Rapid Design of Advanced-Node SoCs

Synopsys customer Aaroh Labs’s expertise in SoC design, post-silicon validation & analog components facilitates innovation in large, complex, multi-core chips.

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Posted in EDA, HPC, Internet of Things, IP

 

How EDA in the Cloud Fuels Semiconductor Innovation

Cloud-based EDA tools are sparking innovation in the semiconductor design industry, learn how they help chip designers meet time, quality, and cost targets.

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Posted in Cloud, EDA, IP