How Cloud IC Verification Reduced DRC Runtimes by 65%
Chip designers are rapidly migrating to EDA tools in the cloud; learn why and explore trends in chip design tools from our panel at SNUG Silicon Valley 2023.
Posted in Cloud, IP, Verification
Chip designers are rapidly migrating to EDA tools in the cloud; learn why and explore trends in chip design tools from our panel at SNUG Silicon Valley 2023.
Posted in Cloud, IP, Verification
Explore the Compute Express Link (CXL) protocol and learn how it uses memory pooling to reduce latency for high-performing computing (HPC) systems via PCIe.
We explain the UFS 4.0 specification for flash storage and explore how data transfer rates up to 5800 MBps enhance smartphones, vehicles, AR/VR, and beyond.
From AI chip design tools to multi-die systems, explore the top trends shared by CEO Aart de Geus during his keynote speech at SNUG Silicon Valley 2023.
Posted in Artificial Intelligence, EDA, Inside Synopsys, IP, Multi-Die Systems
We unpack the Universal Chiplet Interconnect Express (UCIe) standard and explain its benefits for multi-die systems and testing/verification requirements.
Posted in IP, Multi-Die Systems
We explain how the MACsec protocol works as one of the fundamentals of network security, ensuring Ethernet interface security for automotive, HPC and beyond.
Learn how to design security into high-bandwidth DDR memory interfaces and protect DRAM devices & data from memory-scraping attacks like Rowhammer & RAMbleed.
Posted in Internet of Things, IP, Security
We’re advancing development of chiplet-based multi-die systems with a successful UCIe PHY IP tape-out on TSMC’s N3E semiconductor manufacturing process.
Posted in IP, Multi-Die Systems
From chiplet-powered multi-die systems to EDA workflows in the cloud, stay on top of the electronics industry’s latest trends at SNUG Silicon Valley 2023!
Posted in Artificial Intelligence, Cloud, EDA, IP, Multi-Die Systems
Our PCIe 5.0 IP solutions, including digital controllers and PHYs, have passed PCI-SIG 5.0 compliance testing, becoming the first on the 5.0 integrators list.
Posted in IP