We explain chiplets and share how Universal Chiplet Interconnect Express (UCIe) enables multi-die designs for SoC design innovation beyond Moore’s Law.
We explain the multi-chip module packaging types & die-to-die interfaces helping chip designers create high-performance, multi-die designs in the SysMoore Era.
Learn how programmable SmartNICs enable homogeneous data center networking and storage architectures while taking the load off of primary compute resources.
Explore data center history including data volume growth, new data center architectures, hyperscalers, and the influence of high performance computing (HPC).
Posted in HPC
Explore the advantages of data center disaggregation and learn how optical interconnects enable this new architecture with the help of co-packaged optics.
Explore the world of industry standards development and learn how the 800G Ethernet standard impacts high-bandwidth connectivity for networking & data centers.
PCIe 5.0 designs are currently in massive deployment; learn about the standard and explore PCIe 5.0 applications and the importance of silicon-proven IP.
High performance computing continues to expand & evolve; our team shares their 2022 HPC predictions including new HPC applications and processor architectures.
Posted in HPC
Explore the importance of system interoperability in hyperscale data centers and why it matters for AI and high-performance computing (HPC) applications.
We’re looking back at 2021’s breakthroughs & milestones; explore key developments in EDA tools, SoC verification, connected vehicles, and life at Synopsys.