New Horizons for Chip Design

Archive for the 'HPC' Category


How the CXL Standard Improves Latency in High-Performance Computing

Explore the Compute Express Link (CXL) protocol and learn how it uses memory pooling to reduce latency for high-performing computing (HPC) systems via PCIe.

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Posted in HPC, IP


How the MACsec Protocol Keeps Ethernet Networks Secure

We explain how the MACsec protocol works as one of the fundamentals of network security, ensuring Ethernet interface security for automotive, HPC and beyond.

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Posted in 5G, Automotive, Cloud, HPC, IP, Security


Data-Driven World Gets a Lift with First Two-Party PCIe v6.0 Linkup by Synopsys and Keysight

See how we enhanced the PCIe 6.0 specification’s data transfer speed with the industry’s first two-party 64 GT/s linkup through our partnership with Keysight.

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Posted in Artificial Intelligence, Cloud, HPC, IP


Top 5 HPC Trends to Come in 2023

We share our predictions for high performance computing (HPC) in 2023, including the growth of edge computing solutions and the rise of AI and machine learning.

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Posted in Artificial Intelligence, HPC, Machine Learning


A Year in Review: A Recap of Key Technology Advances and Adventures in 2022

We recap 2022 at Synopsys, including cloud-based chip design tools, machine learning and AI-powered EDA solutions, multi-die systems, and secure interface IP.

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Posted in Artificial Intelligence, Cloud, EDA, HPC, Inside Synopsys, IP, Multi-Die Systems, Photonics


What You Need to Know About Reliability, Availability, and Serviceability in High-Performance Computing

Explore the key components of high-performance computing and learn how to design reliability, availability, and serviceability (RAS) into HPC clusters & systems.

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Posted in EDA, HPC, IP


UCIe Heralds a Robust Chiplet Ecosystem for a New Era of SoC Innovation

We explain chiplets and share how Universal Chiplet Interconnect Express (UCIe) enables multi-die designs for SoC design innovation beyond Moore’s Law.

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Posted in Artificial Intelligence, EDA, HPC, Internet of Things, IP, Multi-Die Systems


A Primer on Chip Packaging for Multi-Die Designs

We explain the multi-chip module packaging types & die-to-die interfaces helping chip designers create high-performance, multi-die designs in the SysMoore Era.

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Posted in Artificial Intelligence, HPC, IP, Multi-Die Systems


How Can SmartNICs Move Your Data Center Forward?

Learn how programmable SmartNICs enable homogeneous data center networking and storage architectures while taking the load off of primary compute resources.

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Posted in Cloud, EDA, HPC, IP, Multi-Die Systems, Verification


The Data Center Journey, from Central Utility to Center of the Universe

Explore data center history including data volume growth, new data center architectures, hyperscalers, and the influence of high performance computing (HPC).

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Posted in HPC