What’s Driving the Demand for Chiplets?
Learn how chiplets form the basis of multi-die HPC processor architectures, fueling modern HPC applications and scaling performance & power beyond Moore’s Law.
Sharpen Your Silicon Design Expertise at Synopsys Events this Fall
Fall 2021 silicon design events are almost here! Join us for ARC Processor Virtual Summit, Verification Day 2021, and the Digital Design Technology Symposium.
Posted in 3D-ICs, Artificial Intelligence, Automotive, EDA, HPC, Inside Synopsys, Internet of Things, IP, Machine Learning, Power, Verification
How IP-Enabled SoC Design Is Driving Growth Across All Aspects of Dynamic and Diverse HPC Requirements
Explore how silicon-proven IP for HPC SoC design is driving growth across HPC applications such as network infrastructure, machine learning & AI accelerators.
What Is a Multi-Die Design—and What’s Driving Its Growing Popularity?
Explore the growing popularity of multi-die chip designs and learn how a system-level view helps chip designers reach aggressive PPA targets for data centers.
Posted in 3D-ICs, 5G, Artificial Intelligence, HPC, IP
What’s Driving the Demand for 200G, 400G, and 800G Ethernet?
Hyperscale data centers are driving demand for high-bandwidth Ethernet protocols at speeds up to 800G to support HPC, AI, video streaming, and cloud computing.
Posted in Artificial Intelligence, HPC, IP, Verification
Customer Spotlight: Aaroh Labs Delivers Rapid Design of Advanced-Node SoCs
Synopsys customer Aaroh Labs’s expertise in SoC design, post-silicon validation & analog components facilitates innovation in large, complex, multi-core chips.
Posted in EDA, HPC, Internet of Things, IP
Running a Trillion-Cycle Application Workload with Fast SoC Emulation
Explore the impact of high-performance SoC emulation on chip design & learn how full-visibility debugging gives designers a jump on SoC verification.
Posted in 5G, Artificial Intelligence, Automotive, HPC, Verification
Empowered By Real-World Software to Find Power Bugs
We explain how to find dynamic power & leakage power bugs during SoC verification, using pre-silicon emulation for full-stack system-level power analysis.
Posted in Artificial Intelligence, Automotive, HPC, Power, Verification
How to Achieve High Bandwidth and Low Latency Die-to-Die Connectivity
Die-to-die interfaces in hyperscale data centers require high bandwidth & low latency, learn how this innovation drives modern high-performance computing (HPC).
Posted in 3D-ICs, Artificial Intelligence, HPC, IP
Arm Collaboration Helps You Meet PPA Targets Faster for AI, Cloud, and 5G Infrastructure Chiplets
Explore our collaboration with Arm and learn how our EDA tools help you design chiplets and SoCs while meeting aggressive PPA and time-to-market targets.
Posted in 5G, Artificial Intelligence, Cloud, HPC, IP
