From Silicon To Software

Archive for the 'Artificial Intelligence' Category

 

What Is a Multi-Die Design—and What’s Driving Its Growing Popularity?

Explore the growing popularity of multi-die chip designs and learn how a system-level view helps chip designers reach aggressive PPA targets for data centers.

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Posted in 3D-ICs, 5G, Artificial Intelligence, HPC, IP

 

Why Processor Workloads Are Changing as Moore’s Law Slows

Explore how processor workloads are changing as Moore’s Law slows, driving new processor architectures that meet the performance requirements of modern SoCs.

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Posted in 5G, Artificial Intelligence, IP

 

What’s Driving the Demand for 200G, 400G, and 800G Ethernet?

Hyperscale data centers are driving demand for high-bandwidth Ethernet protocols at speeds up to 800G to support HPC, AI, video streaming, and cloud computing.

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Posted in Artificial Intelligence, HPC, IP, Verification

 

Take the Guesswork Out of Designing Your New Product Architecture

We explain how virtual prototyping eliminates ASIC design bugs before RTL, and how chip architecture design modeling correlates key performance attributes.

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Posted in Artificial Intelligence, Prototyping, Verification

 

AI and AI Chip Design – A New “Chicken and Egg” Riddle

Learn how artificial intelligence is used in the chip design process, helping designers from around the world create better AI chips for growing AI workloads.

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Posted in Artificial Intelligence, EDA

 

Running a Trillion-Cycle Application Workload with Fast SoC Emulation

Explore the impact of high-performance SoC emulation on chip design & learn how full-visibility debugging gives designers a jump on SoC verification.

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Posted in 5G, Artificial Intelligence, Automotive, HPC, Verification

 

Empowered By Real-World Software to Find Power Bugs

We explain how to find dynamic power & leakage power bugs during SoC verification, using pre-silicon emulation for full-stack system-level power analysis.

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Posted in Artificial Intelligence, Automotive, HPC, Power, Verification

 

Why Now Is the Time to Create an AI Strategy for Chip Design

Learn how designers increase productivity with AI chip design tools and improve chip performance & energy efficiency to meet PPA targets on complex designs.

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Posted in Artificial Intelligence, EDA

 

How to Achieve High Bandwidth and Low Latency Die-to-Die Connectivity

Die-to-die interfaces in hyperscale data centers require high bandwidth & low latency, learn how this innovation drives modern high-performance computing (HPC).

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Posted in 3D-ICs, Artificial Intelligence, HPC, IP

 

Customer Spotlight: Tachyum’s Universal Processor for Hyperscale Data Centers

Synopsys customer Tachyum’s new Prodigy processor is set to transform hyperscale data centers, making AI & high-performance computing (HPC) more accessible.

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Posted in Artificial Intelligence, IP