Explore the history of FPGA prototyping in the SoC design/verification process and learn about HAPS-100, a new prototyping system for complex AI & HPC SoCs.
Synopsys and IBM Research: Driving Real Progress in Large-Scale AI Silicon and Implementing a Hybrid Cloud Model for Chip Design
Hybrid Cloud architecture enables innovation in AI chip design; learn how our partnership with IBM combines the best in EDA & HPC to improve AI performance.
We explore how EDA tools enable hyper-convergent IC designs, supporting the PPA and yield targets required by advanced 3DICs and SoCs used in AI and HPC.
Power analysis is key to the SoC design process; learn how emulation solutions deliver actionable power verification results in hours to help meet PPA targets.
Learn how AI & neural networks enhance digital image processing for sharper, more vivid images, and how dedicated SoCs boost embedded vision applications.
3D ICs help SoC designers extend the design scale beyond Moore’s Law; learn how unified 3D IC design tools enable faster convergence for multi-die chips.
With DVCon 2021 on the horizon we share a primer on our datapath verification technology HECTOR, exploring its impact on machine learning & AI chip design.
We explain how AI chip designers can address SoC glitch power & reduce hardware power consumption early in the design cycle by leveraging chip design tools.
Learn how electronic design automation (EDA) tools & silicon-proven IP enable today’s most influential smart tech, including ADAS, 5G, IoT, and Cloud services.
Learn how AI accelerators enable greater scalability & lower latency when processing artificial intelligence workloads both in hyperscale data centers & SoCs.
Posted in Artificial Intelligence