We share our predictions for high performance computing (HPC) in 2023, including the growth of edge computing solutions and the rise of AI and machine learning.
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Posted in Artificial Intelligence, HPC, Machine Learning
Explore the impact of AI and ML on the chip design industry and learn how chiplet-enabled multi-die systems solve processing, memory, and bandwidth limitations.
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Posted in Artificial Intelligence, EDA, Multi-Die Systems
President & COO Sassine Ghazi explained how AI can transform chip design flows into autonomous design instruments during his 2022 AI Hardware Summit keynote.
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Posted in Artificial Intelligence, EDA, Machine Learning
We recap 2022 at Synopsys, including cloud-based chip design tools, machine learning and AI-powered EDA solutions, multi-die systems, and secure interface IP.
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Posted in Artificial Intelligence, Cloud, EDA, HPC, Inside Synopsys, IP, Multi-Die Systems, Photonics
See how silicon remastering eases the chip supply shortage by migrating old designs to modern process nodes to expand semiconductor manufacturing capacity.
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Posted in Artificial Intelligence, EDA
Learn how our partnership with SiMA.ai enables embedded edge machine learning applications with programmable processor IP cores and a software-driven ML SoC.
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Posted in Artificial Intelligence, Customer Spotlight, IP
See how virtual prototyping, chip verification, and EDA tools helped Neuchips design an AI accelerator chip for the deep learning recommendation model (DLRM).
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Posted in Artificial Intelligence, Customer Spotlight, IP, Verification
Alongside AI-enabled SoC design tools, our QuickStart Implementation Kits help chip designers develop high-performance processors for embedded applications.
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Posted in 5G, Artificial Intelligence, Automotive, IP
We explain chiplets and share how Universal Chiplet Interconnect Express (UCIe) enables multi-die designs for SoC design innovation beyond Moore’s Law.
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Posted in Artificial Intelligence, EDA, HPC, Internet of Things, IP, Multi-Die Systems
We explain the multi-chip module packaging types & die-to-die interfaces helping chip designers create high-performance, multi-die designs in the SysMoore Era.
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Posted in Artificial Intelligence, HPC, IP, Multi-Die Systems