3 min read/ Aug 12, 2025 AI at the Edge: Synopsys Collaborates with Thai Embedded Systems Association to Advance AIoT Innovation By Adrian Ng Tags: AI & Machine Learning, RISC-V, Prototyping, Chip Design Insights, Design, Internet of Things, Energy-Efficient SoCs, Processor Solutions, Silicon IP
3 min read/ Aug 11, 2025 AI Vision: Creating Chips Today for Tomorrow’s Cars and Robots By Kevin Wei Tags: AI & Machine Learning, Prototyping, Chip Design Insights, Design, Emulation, Automotive, Processor Solutions, Silicon IP, Verification
3 min read/ Aug 07, 2025 Simplifying AI Chip Development: Arm and Synopsys Execs Discuss Chiplet, Subsystem, and IP Integration By Frank Malloy Tags: Multi-Die, AI & Machine Learning, Chip Design Insights, Design, Physical Implementation, Silicon IP, Verification, Virtual Prototyping
5 min read/ Jun 10, 2025 Software-Defined Vehicles: Agile Development with Cloud-Based Virtual Prototypes By Gunnar Braun, Stewart Williams Tags: Cloud, Insights, Chip Design Insights, Automotive, Cloud Insights, Verification, Virtual Prototyping
5 min read/ Jun 04, 2025 Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles By Tom De Schutter Tags: Cloud, Chip Design Insights, Design, Verification IP, Automotive, Verification, Virtual Prototyping
3 min read/ May 22, 2025 Faster, More Collaborative SoC and Chiplet Architecture Exploration: Introducing Synopsys Platform Architect Development Kit (PADK) By Kamal Desai Tags: Verification Central, Cloud, Multi-Die, Prototyping, Chip Design Insights, Design, Verification, Virtual Prototyping
3 min read/ Aug 05, 2025 UCIe 3.0 Is Here: Synopsys IP Solutions Are Ready By Varun Agrawal Tags: Multi-Die, Chip Design Insights, Design, Interface IP, Silicon IP
5 min read/ Jul 01, 2025 RTL Signoff vs. Functional Signoff: What’s the Difference? By Bradley Geden, Manoz Palaparthi Tags: Verification Central, Multi-Die, RTL Synthesis, Static & Formal Verification, AI & Machine Learning, Debug, Physical Verification, Test, Simulation, Energy-Efficient SoCs, Signoff, Chip Design Insights, Design, Verification, Formal Verification
3 min read/ May 28, 2025 High Bandwidth Memory (HBM) at the AI Crossroads: Customization or Standardization? By Synopsys Editorial Staff Tags: Verification Central, Multi-Die, AI & Machine Learning, Memory, Chip Design Insights, Design, Interface IP, Verification IP, HPC, Data Center, Silicon IP, Verification, 3DIC Design