From Silicon To Software

Archive for the '3D-ICs' Category

 

How 3DICs Are Sparking a New Wave of Product Innovation

Explore the multi-die 3DIC technology that’s helping chip designers meet growing compute demands, including chiplets, 3D stacking, nanosystems, and more.

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Posted in 3D-ICs

 

UCIe Heralds a Robust Chiplet Ecosystem for a New Era of SoC Innovation

We explain chiplets and share how Universal Chiplet Interconnect Express (UCIe) enables multi-die designs for SoC design innovation beyond Moore’s Law.

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Posted in 3D-ICs, Artificial Intelligence, EDA, HPC, Internet of Things, IP

 

A Primer on Chip Packaging for Multi-Die Designs

We explain the multi-chip module packaging types & die-to-die interfaces helping chip designers create high-performance, multi-die designs in the SysMoore Era.

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Posted in 3D-ICs, Artificial Intelligence, HPC, IP

 

How Can SmartNICs Move Your Data Center Forward?

Learn how programmable SmartNICs enable homogeneous data center networking and storage architectures while taking the load off of primary compute resources.

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Posted in 3D-ICs, Cloud, EDA, HPC, IP, Verification

 

What It Takes to Design SoCs for the SysMoore Era

Learn how SoC design is influenced by 3DICs, system-of-chips, hyper-convergent chip designs, and AI-enabled EDA tools in the SysMoore era of chip design.

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Posted in 3D-ICs, Artificial Intelligence, EDA

 

A Year in Review: A Recap of Key Milestones and Moments in 2021

We’re looking back at 2021’s breakthroughs & milestones; explore key developments in EDA tools, SoC verification, connected vehicles, and life at Synopsys.

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Posted in 3D-ICs, Automotive, EDA, HPC, Inside Synopsys, IP, Prototyping, Quantum Computing, Verification

 

5 Things You Need to Know About Hyper-Convergent Chip Designs

Explore the latest on hyper-convergent chip designs, IC hyperconvergence, and the EDA tools enabling 3DICs and more in the SysMoore era of semiconductor design.

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Posted in 3D-ICs, EDA, IP

 

What’s Driving the Demand for Chiplets?

Learn how chiplets form the basis of multi-die HPC processor architectures, fueling modern HPC applications and scaling performance & power beyond Moore’s Law.

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Posted in 3D-ICs, HPC

 

Sharpen Your Silicon Design Expertise at Synopsys Events this Fall

Fall 2021 silicon design events are almost here! Join us for ARC Processor Virtual Summit, Verification Day 2021, and the Digital Design Technology Symposium.

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Posted in 3D-ICs, Artificial Intelligence, Automotive, EDA, HPC, Inside Synopsys, Internet of Things, IP, Machine Learning, Power, Verification

 

What Is a Multi-Die Design—and What’s Driving Its Growing Popularity?

Explore the growing popularity of multi-die chip designs and learn how a system-level view helps chip designers reach aggressive PPA targets for data centers.

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Posted in 3D-ICs, 5G, Artificial Intelligence, HPC, IP