We share AI chip design insights from AI Hardware Summit 2021, including wafer scale AI accelerator chips, high-bandwidth memory interfaces, and custom SoCs.
Stelios Diamantidis leads strategy and product management for Synopsys AI, and is a founder of the Machine Learning Center of Excellence, where he looks at applying machine learning (ML) technology to key disruptions in the design and manufacturing of integrated computational systems. He has more than 20 years of experience in system and semiconductor design and EDA software. A passionate technologist, Stelios has pioneered several EDA applications including design verification IP (2001), constrained-random metric-driven verification (2003), design-for-test (DFT) verification (2005), and at-speed post-silicon validation (2007). He has also driven the definition of IEEE standards including IEEE1647 (vice chair, Standard for Functional Verification Language) and IEEE1687 (founding member, Standard for Access and Control of Instrumentation). Stelios has published numerous papers and articles on the design and test of semiconductors and routinely presents at industry conferences and events. He holds an M.S. degree in electrical engineering from Stanford University.
Posts by Stelios Diamantidis:
Learn how designers increase productivity with AI chip design tools and improve chip performance & energy efficiency to meet PPA targets on complex designs.
Learn how AI accelerators enable greater scalability & lower latency when processing artificial intelligence workloads both in hyperscale data centers & SoCs.
Posted in Artificial Intelligence
By Stelios Diamantidis, Director, AI Products, Design Group