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Author Archive
Rimpy Chugh
rimpychugh


Posts by Rimpy Chugh:

 

Don’t Let the Bugs Bite: Reducing Design Reworks and Errors with Advanced Linting (Part 1)

Learn how advanced code linting accelerates the RTL & SoC design flow, testing for and verifying functional chip design issues before testbenches are available.

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Posted in Verification

 

Don’t Let Faults in the Field Spoil Safety-Critical Designs

We explore how integrating functional verification and fault simulation techniques helps protect safety-critical chip designs from faults in the field.

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Posted in Verification

 

How Are Fault Simulation Technologies Keeping Pace with Growing Chip Complexity?

Learn how fault simulation techniques are evolving to meet growing chip design complexity, including unified functional safety verification platforms.

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Posted in Verification

 

Integration Challenges for Multi-Billion Gate ASICs: Part 3 – Static Linting

Explore the challenges of static linting of code and learn how static linting tools speed up the ASIC development process for faster chip design signoff.

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Posted in Verification

 

Integration Challenges for Multi-Billion-Gate ASICs: Part 1 – Clock Domain Crossing

We explain clock domain crossing & common challenges faced during the ASIC design flow as chip designers scale up CDC verification for multi-billion-gate ASICs.

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Posted in Verification