We explain chiplets and share how Universal Chiplet Interconnect Express (UCIe) enables multi-die designs for SoC design innovation beyond Moore’s Law.
Dr. Manuel Mota joined Synopsys in 2009 as a product marketing manager and is responsible for the DesignWare® Data Converter, High-Speed SerDes, and Bluetooth IP product lines. He brings more than 18 years of technical and marketing experience to his position. Prior to Synopsys, Manuel held product marketing, business development, and IP design positions at MIPS Technologies and Chipidea Microelectronica. Manuel holds a Ph.D. in electronic engineering from Lisbon Technical University, which he completed while working at CERN (Switzerland) as a research fellow. He has authored multiple technical papers and presented in several technical conferences on analog and mixed-signal design.
Posts by Manuel Mota:
We explain the multi-chip module packaging types & die-to-die interfaces helping chip designers create high-performance, multi-die designs in the SysMoore Era.
Explore the growing popularity of multi-die chip designs and learn how a system-level view helps chip designers reach aggressive PPA targets for data centers.
Die-to-die interfaces in hyperscale data centers require high bandwidth & low latency, learn how this innovation drives modern high-performance computing (HPC).