Meeting Requirements for UCIe-Based Multi-Die Systems Success
We unpack the Universal Chiplet Interconnect Express (UCIe) standard and explain its benefits for multi-die systems and testing/verification requirements.
Posted in IP, Multi-Die Systems
Manuel Mota
Dr. Manuel Mota joined Synopsys in 2009 as a product marketing manager and is responsible for the DesignWare® Data Converter, High-Speed SerDes, and Bluetooth IP product lines. He brings more than 18 years of technical and marketing experience to his position. Prior to Synopsys, Manuel held product marketing, business development, and IP design positions at MIPS Technologies and Chipidea Microelectronica. Manuel holds a Ph.D. in electronic engineering from Lisbon Technical University, which he completed while working at CERN (Switzerland) as a research fellow. He has authored multiple technical papers and presented in several technical conferences on analog and mixed-signal design.
Posts by Manuel Mota:
Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process
We’re advancing development of chiplet-based multi-die systems with a successful UCIe PHY IP tape-out on TSMC’s N3E semiconductor manufacturing process.
Posted in IP, Multi-Die Systems
How Does Short-Reach Connectivity Transcend Physical and Power Limits?
Learn how Very Short-Range (VSR) connectivity & optical interconnects manage growing data center traffic by reducing power consumption & boosting bandwidth.
Posted in IP, Optical Design
UCIe Heralds a Robust Chiplet Ecosystem for a New Era of SoC Innovation
We explain chiplets and share how Universal Chiplet Interconnect Express (UCIe) enables multi-die designs for SoC design innovation beyond Moore’s Law.
Posted in Artificial Intelligence, EDA, HPC, Internet of Things, IP, Multi-Die Systems
A Primer on Chip Packaging for Multi-Die Designs
We explain the multi-chip module packaging types & die-to-die interfaces helping chip designers create high-performance, multi-die designs in the SysMoore Era.
Posted in Artificial Intelligence, HPC, IP, Multi-Die Systems
What Is a Multi-Die Design—and What’s Driving Its Growing Popularity?
Explore the growing popularity of multi-die chip designs and learn how a system-level view helps chip designers reach aggressive PPA targets for data centers.
Posted in 5G, Artificial Intelligence, HPC, IP, Multi-Die Systems
How to Achieve High Bandwidth and Low Latency Die-to-Die Connectivity
Die-to-die interfaces in hyperscale data centers require high bandwidth & low latency, learn how this innovation drives modern high-performance computing (HPC).
Posted in Artificial Intelligence, HPC, IP, Multi-Die Systems
