Explore AI chip architecture and learn how AI’s requirements and applications shape AI optimized hardware design across processors, memory chips, and more.
Learn how AI-enabled EDA tools accelerate the SoC design verification flow and chip debug cycle for first-time-right chip designs and faster time-to-market.
We explain computational lithography and explore how our partnership with NVIDIA accelerates semiconductor scaling and the chip design flow in the AI age.
Learn how to design security into high-bandwidth DDR memory interfaces and protect DRAM devices & data from memory-scraping attacks like Rowhammer & RAMbleed.
We’re advancing development of chiplet-based multi-die systems with a successful UCIe PHY IP tape-out on TSMC’s N3E semiconductor manufacturing process.
From chiplet-powered multi-die systems to EDA workflows in the cloud, stay on top of the electronics industry’s latest trends at SNUG Silicon Valley 2023!
We explain how artificial intelligence (AI) changes the chip design flow, enhancing EDA tools and helping silicon design engineers improve productivity and PPA.
Learn the basics of battery design, including battery modeling and simulation tools and the hunt for new battery materials for electric vehicles and beyond.
We explain how cloud-based hardware IP verification saves valuable time in the hardware design flow by automating SoC simulation and reducing time to debug.
Learn how to optimize the RTL design flow with real-time PPA analysis and chip design insights from physically aware RTL analysis and automated debug tools.