By Vikram Bhatia, Head, Synopsys Cloud Go-to-Market and Product Strategy
In recent years, many semiconductor companies have successfully shifted chip design from on-premises data centers to the cloud. With monolithic systems on chips (SoCs) and multi-die systems becoming ever-more complex, chip designers increasingly rely on “unlimited” cloud resources and new cloud-native, AI-driven EDA tools to rapidly optimize power, performance, and area (PPA).
Unsurprisingly, cloud-based chip design was the subject of numerous sessions and tracks at the Synopsys Users Group (SNUG) Silicon Valley 2023 conference, including a panel titled “Harnessing the Power of the Cloud: Is the Ecosystem Ready?” During the session, industry experts identified the following four trends driving the rapid migration of EDA tools and chip design workloads to the cloud:
Read on to learn about key takeaways from the panel experts—and get an in-depth look at how cloud-native EDA tools and pre-optimized hardware platforms are empowering semiconductor companies to accelerate their chip design cycles.
Ansys CTO Prith Banerjee got the discussion going by describing the real-world benefits of scaling up in the cloud to meet the compute-intensive demands of chip design workloads. Ansys, said Banerjee, leverages high-performance computing (HPC) to render incredibly complex simulations that enable semiconductor companies to accurately analyze electrical and thermal interactions for billions of instances on monolithic SoCs and multi-die systems.
As Banerjee pointed out, chip design simulation workloads typically require massive amounts of parallel processing power provided by GPU clusters and large shared memory pools. Accessing this infrastructure in the cloud—and on demand—allows customers to pay only for the resources they need on a per project basis. Moreover, cloud vendors continuously upgrade their hardware with the latest GPUs and CPUs, purpose-built AI accelerators, and newest memories.
Dermot O’Driscoll, vice president of product solutions at Arm, expressed similar sentiments, noting that designing and verifying new chips requires a huge amount of compute power. The cloud, said O’Driscoll, offers Arm a viable alternative to obtaining this compute capacity while reducing its global data center footprint. According to O’Driscoll, over 50% of Arm’s EDA workloads now take place in the cloud, allowing engineers to scale up and efficiently run hundreds of thousands of concurrent jobs.
However, O’Driscoll emphasized more cycles isn’t always better, even if they are readily available in the cloud. O’Driscoll said he sees AI-driven EDA tools enabling semiconductor companies to further streamline chip design workflows by intelligently analyzing and managing processes in real time. O’Driscoll adds EDA vendors are already doing a “fantastic job” of optimizing cloud-based chip design with sophisticated ML models that help semiconductor companies PPA targets faster.
Phil Steinke, CAD infrastructure and physical design fellow at AMD, said AMD’s EDA hybrid cloud strategy allows the semiconductor company to accelerate chip design and verification while speeding time to market for next-gen silicon. Steinke also spotlighted the role of AMD EPYC processors in cloud-driven EDA, noting Microsoft Azure HBv4-series virtual machines harness AMD’s powerful silicon for many HPC workloads, including rendering, computational geoscience, and financial risk analysis. In addition to tapping massive amounts of compute power, Steinke said AMD leverages Microsoft Azure to optimize and streamline its chip development software environment.
Preeth Chengappa, head of industry, semi, and EDA at Microsoft, qualified Steinke’s optimization remarks by pointing out that Synopsys customers running EDA tools on Microsoft Azure are seeing productivity increases of up to 35%. Chengappa also said designing chips in the cloud will ultimately become more cost-effective as cross-industry collaboration increases and full-stack, AI-driven EDA tools continue to evolve. Lastly, Chengappa highlighted the positive role EDA companies are playing in lowering costs and accelerating time to market—and emphasized ongoing optimization initiatives should go far beyond “lift and shift.”
Sandeep Mehndiratta, Synopsys senior vice president for enterprise go-to-market, concurred. Lift and shift—or simply porting on-premises tools to the cloud—isn’t a viable option for EDA and chip design workflows. That’s why Synopsys offers cloud-native EDA tools and pre-optimized hardware platforms, as well as flexible SaaS (software as a service) and (bring your own cloud) BYOC deployment options. As Mehndiratta explained, combining the availability of advanced compute with unlimited access to on-demand EDA software licenses enables semiconductor companies to design chips more efficiently while speeding time to market.
The security benefits of cloud-based EDA design were also discussed in-depth during the SNUG Silicon Valley panel. As Chengappa recalled, the semiconductor industry once saw security as the single biggest obstacle to moving EDA tools and workflows to the cloud. These days, said Chengappa, cloud-based security is widely considered ironclad for EDA and other sensitive applications. Chengappa pointed out that Microsoft spent billions of dollars to build advanced cybersecurity centers to protect against evolving threats and meet strict international security protocols. In addition, Chengappa confirmed semiconductor companies now leverage the security and performance capabilities of Microsoft Azure to design and verify chips for the U.S. Department of Defense (DoD).
O’Driscoll concurred with Chengappa’s description of robust cloud security, noting cloud vendors maintain an impressively high level of expertise and discipline. Cloud vendors, said O’Driscoll, meticulously document and implement stringent security processes to deal with cyber threats such as ransomware and zero-day exploits. O’Driscoll acknowledged the semiconductor industry will always face new cybersecurity challenges—whether in the cloud or on-premises—due to a dynamic threat landscape. Nevertheless, O’Driscoll reiterated security concerns no longer prevent chip companies from adopting cloud-based EDA tools for design, verification, testing, and manufacturing.
Dan Kochpatcharin, head of TSMC’s design infrastructure management division, said securing and protecting customer IP have always been top priorities for the dedicated IC foundry. Kochpatcharin referenced TSMC’s Open Innovation Platform® Virtual Design Environment (OIP VDE), which enables customers to securely design silicon on Microsoft Azure, Amazon Web Services (AWS), and Google Cloud Platform. As Kochpatcharin explained, TSMC works closely with its OIP partners like Synopsys to ensure its OIP VDE-based EDA tools and customer data—such as process technology files, process design kits (PDKs), foundation IP, and reference flows—are stored and protected in highly secure environments.
Ronen Schwartz, senior vice president and general manager of cloud storage at NetApp, said he agreed security concerns are no longer an impediment to cloud adoption. Indeed, the opposite is now true, as companies choose the secure capabilities of the cloud to store and archive sensitive data that must remain immutable. Schwartz confirmed many organizations are implementing a hybrid cloud model, with certain applications and workloads moving to the cloud while other tools and workflows remain on-premises.
As new process nodes lead to an explosion of chip design data—3nm processes require four times the storage capacity and computation capabilities of 5nm—the cloud is helping semiconductor companies efficiently meet demands for more secure, flexible, and cost-effective storage options. Fortunately, companies can now choose cloud-based storage options to simultaneously match budget and performance requirements.
Cloud-based storage, said Schwartz, will continue to evolve as new AI/ML tools further optimize data retrieval and help customers manage costs in real time. Ultimately, storage will be as easy to navigate as driving with a GPS, Schwartz concluded.
More than 1,000 engineers recently gathered at the Santa Clara Convention Center to attend SNUG Silicon Valley 2023. The world’s biggest annual chip design users event offers attendees many opportunities to learn about the latest semiconductor technology and trends, from CXL 3.0 and machine learning (ML) to multi-die systems and cloud-native EDA tools. Catch up on highlights from the conference by reading these blog posts: