Power semiconductor devices are at the heart of modern electronics, powering everything from smartphones to automobiles. These tiny high-voltage and high-current components are designed with meticulous care and attention to detail, and any errors in their design can lead to costly mistakes during fabrication. Growing demands from the portable and smart electronics market to constantly evolving high-performance computing systems place significant pressure on the power semiconductors to be utterly reliable and longer lasting.
The longer you expect an electronic device to work, the more investment goes into figuring out the best device material, device size, and the type of circuit you need to create. A good solution/platform is necessary to perform all the necessary steps in the process.
Along with power devices, another crucial step in the IC design process is electrical layout verification, which involves checking the integrity of the circuit against unconventional scenarios. These reliability checks are performed to understand if a circuit can withstand electrostatic discharge events without sustaining any damage or performance degradation. As chip designs grow larger and more complex, the number of unknowns increases, and designers must solve for more scenarios. Teams typically solve problems sequentially, which requires a lot of time and iterations. Today, both power device design and ESD verification are very ad-hoc processes, and designers are stitching together a variety of solutions to achieve their desired goal.
Our acquisition of Silicon Frontline Technology will enable us to immediately address critical performance and reliability challenges in the IC design process and offer end-to-end solutions for all electrical layout verification needs. In addition, Synopsys has gained core technologies to accelerate development of comprehensive system analysis solutions.
To learn more about what Silicon Frontline Technology will bring to Synopsys customers, we chatted with Hitesh Patel, senior director of product management for signoff solutions in the Synopsys EDA Group.
A: Silicon Frontline Technology provides a unique electrical layout verification solution that addresses one of the most critical yet difficult to solve performance and reliability challenges in today’s complex electronic designs. Its solutions detect “blind spots” in the design of large-scale power semiconductor devices and electrostatic discharge (ESD) protection networks, providing accurate optimization and validation early in the cycle for first-silicon success. Design teams benefit from accurate and fast resistance, capacitance, thermal, and ESD verification at pre- and post-layout. For power devices as well as mixed-signal and analog designs, Silicon Frontline’s products are the de facto standard, enabling engineers to improve efficiency and ensure robustness of their designs.
This acquisition enables Synopsys to extend the capabilities of our design analysis portfolio and help build out a system-level electrical analysis platform. We also gain a robust framework that enables retargeting of the core engines for system-level signoff analysis of 3DICs, thermal, and electromigration.
A: Firstly, Silicon Frontline’s Dynamic ESD Simulation solution complements the static ESD technology in Synopsys IC Validator™ PERC physical verification solution, creating the best overall ESD verification solution in the market. Static and dynamic ESD analysis is rapidly emerging as a critical and mandatory need for advanced nodes.
Secondly, Silicon Frontline’s electro-thermal solution accelerates our investments in power design technology co-optimization (DTCO) technologies focused on reducing the development cycles in the design of power transistors. Power devices remain the heart of most electronics, and power device design and analysis is a crucial part of SoC power signoff.
Lastly, Silicon Frontline’s 3D solvers provide a unique opportunity to accelerate development of thermal solutions, significantly advancing our initiatives for comprehensive multi-die systems analysis, photonics, and future beyond-CMOS technologies.
A: Left unabated, ESD can severely damage silicon chips, and addressing ESD issues is a key requirement for enhancing reliability. Historically, designers have created their own ad-hoc ESD rules to check, using one set of tools for static checks and another for dynamic checks. With this acquisition, Synopsys will be able to provide one platform with complete coverage for ESD as well as for electrothermal analysis, with unified methods for addressing the thermal, signal integrity, and power integrity aspects of system design simultaneously.
In addition to ESD analysis, the acquisition also brings solutions for fast 3D extraction, point-to-point resistance calculation, static EMIR analysis, power device DC simulation, power device gate network extraction and simulation, dynamic device model generation, and electrothermal simulation.
With our chip design expertise, Synopsys offers the unique approach of addressing a design starting from the chip level and then moving into the system level, rather than the other way around. This enables us to help designers optimize their designs from the inside out, so to speak, which yields better power, performance, and area (PPA) outcomes as well as productivity. We look forward to welcoming the Silicon Frontline team—with its 300+ years of computational geometry, complex numerical methods, and semiconductor material expertise—to Synopsys. Product roadmaps will be aligned as the acquisition becomes final.