Achieving predictable chip design closure has become progressively challenging for teams worldwide. While linting tools have existed for decades, traditional tools require significant effort to filter out the noise and eventually zero-in on the real design issues. With increasing application specific integrated circuit (ASIC) size and complexity, chip designers require higher debug efficiency when managing a large number of violations in order to ultimately achieve a shorter turnaround time (TAT).
In the first two parts of this linting series, we established how linting offers a comprehensive mechanism to check for fundamental chip design faults and touched on the many benefits of having a guiding methodology for deeper functional lint analysis.
Recognizing the disparities between in-house coding styles, our extensive experience of working with industry leaders has given us an edge to accelerate RTL and system-on-chip (SoC) design flow for customers previously unseen. Solutions such as Synopsys VC SpyGlass™ CDC have already proven how valuable advanced machine learning (ML) algorithms are to achieve SoC design signoff with scalable performance and high debug productivity. Leveraging industry-standard practices and our decades of expertise, the latest offering of Synopsys VC SpyGlass Lint now includes powerful ML capabilities to significantly improve debug efficiency for designers.
In the finale of this blog series, we’ll cover the downside of traditional linting tools, how the functionality of ML and root-cause analysis (ML-RCA) accelerate design signoff, the key benefits of Synopsys VC SpyGlass Lint, and where we see the future of smart linting headed.
The “rule of 10” states that it is 10 times costlier and harder to find and fix a bug as one moves from pre-silicon to post-silicon. Conventionally, traditional lint EDA tools deliver more noise in designs because RTL lint checks identify design violations statically.
Traditional lint flows rely on manual debug requiring designers to debug violations one-by-one, a highly inefficient approach leading to repeated and unnecessary cycles. For teams handling multi-million-gate SoC designs, lint signoff can take several weeks. Designers therefore need an intelligent way to scale the debug cycle and gain assistance to nail down the real gaps in the design.
The drawbacks in traditional linters drive the need for comprehensive ML-powered linting technology which, when combined with integrated formal engines, can enable a true shift left for the entire development lifecycle and help designers make quick judgements about flagged violations.
In Part 1, we talked about how functional lint analysis provides users with a clean lint result, helps them reduce design issues identified later in the design cycle, and flags advanced checks such as livelock, deadlock, deadcode, and more. When it comes to ML-powered linting, there is one important approach that designers need to keep top of mind: efficient violation clustering based upon similar root causes.
Simply put, the goal of the clustering approach is to determine a cause-and-effect relationship. By integrating ML with the method of clustering, an automatic root-cause analysis (RCA) is done to group all violations caused by a common root cause in a design. Based on the classification, each violation is mapped against the exact root cause, enabling the designer to determine why they exist and if the presence of similar violations is triggered by a single root cause.
For instance, imagine there are 100,000 violations present in a design during a standard lint run. When using Synopsys VC SpyGlass ML-RCA during the run, these 100,000 violations get grouped into 50 clusters where each cluster includes 20,000 violations (100,000 divided by 50), all of which have a common root cause. The cluster then features debug aids addressing the reason behind it causing 20,000 violations.
Violations can either have multiple root causes or multiple root causes that can point to a single violation. In the case of Synopsys VC SpyGlass Lint (as shown in the figure above), these raw input violations analyze 100,000 violations and use the integrated ML algorithms to develop each cluster, all while identifying and establishing a cause-and-effect relationship. The tool infers the root cause automatically for any design and narrows down the relationship between multiple violations without requiring domain expertise or training data. With this unique approach, users can quickly resolve thousands of violations clustered in one group using ML-RCA and be set up for success from Day 1— a dream come true for the EDA community.
With the benefits we’re unravelling with ML-powered advanced linting and integrated formal engines, the possibilities are endless. Companies no longer need to figure out how to invest valuable resources and time in developing specialized expertise and instead can rely on solutions like Synopsys VC SpyGlass Lint to quickly verify some of the most complex of SoC designs.
Going forward, we will continue to invest in our vast rule selections for automotive and other emerging applications, while guiding customers to shift left and build methodologies that boost the growth of next-generation designs and address time-to-market needs. As design scope and sizes increase, we are hopeful that our efforts will present more use cases for the technology and can say with certainty that smart linting will become more important than it has ever been in years to come.
Catch up on other blog posts for more insights on linting: