As Synopsys and TSMC collaborate to deliver high-quality IP on TSMC’s advanced FinFET processes, Synopsys announces a successful tape-out of the Universal Chiplet Interconnect Express™ (UCIe™) PHY IP on the TSMC N3E process. UCIe IP is a key element of multi-die systems, enabling designers to achieve secure and robust die-to-die connectivity in a package while delivering high bandwidth, low power, and low latency.
“TSMC works closely with Synopsys to drive semiconductor advancements that pave the way to sophisticated new electronic products for a wide range of applications,” said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. “The tapeout of the Synopsys UCIe PHY IP on our most advanced N3E process is the latest milestone in our longstanding collaboration, helping design teams realize the key benefits of multi-die systems. The development of the UCIe PHY IP in TSMC’s N3E process supports 3D IC designs that use the TSMC 3DFabric™, our comprehensive family of 3D silicon stacking and advanced packaging technologies.”
“As multi-die systems move into the mainstream of the semiconductor world, UCIe technology will play an integral role in their success,” said Dr. Debendra Das Sharma, chairman at the UCIe Consortium, which oversees the standard’s development and evolution. “We’re excited to see our members develop solutions that will help drive adoption of the standard and create a robust die-to-die connectivity solution.”
Multi-die systems—integration of heterogeneous dies, or chiplets—are an answer to the rising systemic and scaling complexities that are threatening to curb the transformative promise of applications like high-performance computing (HPC), AI, and automotive. By integrating multiple dies in a single package, designers can efficiently deliver innovative products with unprecedented functionality, reuse proven dies to reduce risk, accelerate time to market, and rapidly create new product variants with optimized system power and performance. A variety of factors—from the emergence of advanced packaging to the availability of standards-based IP and chip design and verification tool flows optimized for such architectures—has converged to ease the development of multi-die systems.
2023 is on tap to be a big year for multi-die systems, as demand for this type of architecture increases while the ecosystem supporting it continues to grow and mature. Working closely with the ecosystem, Synopsys delivers a comprehensive solution, encompassing IP and EDA tools, to ease the development of these systems.
What differentiates UCIe from other emerging die-to-die specifications is that it defines a complete stack for the die-to-die interconnect. This ensures interoperability of compliant devices. The standard offers very compelling performance metrics and supports advanced packages (silicon interposer, silicon bridge, and RDL fanout) as well as standard packages (organic substrate and laminate). Of the three stack layers that UCIe covers, the PHY is the layer that provides the electrical interface to the package media.
For monolithic SoCs, the design process is traditionally sequential, from IP to chip to package. In the multi-die system world, a holistic approach is necessary to address all the interdependencies. In other words, there’s a very close correlation between the design of the die interface and of the package in which it will be used. The Synopsys UCIe PHY IP has a flexible architecture that supports advanced and standard packaging technologies, providing up to 5Tbps/mm bandwidth efficiency. It’s part of a complete UCIe solution that includes controller IP as well as verification IP. Synopsys UCIe Controller IP supports popular protocols such as PCI Express and CXL and enables secure, low-latency NoC-to-NoC links with streaming protocols. Synopsys UCIe Verification Solution, Verification IP, and Transactors for simulation and hardware-assisted platforms, including Synopsys ZeBu® emulation system and Synopsys HAPS® prototyping solution, help accelerate verification closure of UCIe-based interconnected systems.
The UCIe PHY IP is co-developed with the Synopsys 3DIC Compiler platform to deliver a dedicated implementation that automates UCIe routing for 2.5D heterogeneous integration, accelerating productivity.
As a member of the UCIe Consortium, Synopsys contributes to the development of the specification alongside other industry leaders. Our expertise in multi-die system architectures is exemplified by our comprehensive Multi-Die System Solution, which is designed to accelerate integration of heterogeneous dies. Synopsys continues to collaborate with TSMC to align our UCIe IP for other process nodes and packaging technologies and also with other major foundries on similar efforts. Our IP portfolio provides a full slate of die-to-die IP solutions, including 112G XSR controller and PHY IP and Advanced Interface Bus (AIB) PHY IP.
Compute-hungry applications are driving demand for monolithic SoCs, yet these devices are hitting a manufacturability limit. Multi-die systems offer a solution, providing accelerated, cost-effective scaling of system functionality, along with reduced risk, time to market, and system power. With several dozen multi-die system designs on our radar, it’s clear that this architecture is quickly becoming the architecture of choice, especially for teams designing for HPC, hyperscale data centers, highly automated vehicles, and mobile devices.
UCIe is one of the many advanced technologies that have emerged to provide a foundation for multi-die systems. By ensuring interoperability, UCIe stands ready to pave a smoother path forward for a truly open multi-die ecosystem.
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