By Richard Solomon, Sr. Staff Technical Product Manager, and Gary Ruggles, Sr. Staff Product Manager, Synopsys Solutions Group
PCI Express® (PCIe®) is the most widely adopted and extensible interconnect technology in history. As the leading supplier of IP solutions for PCIe, I am thrilled to announce that Synopsys IP solutions for PCIe 5.0, including digital controllers and PHYs, have officially passed PCI-SIG 5.0 Compliance Testing and are the first IP to be listed on the 5.0 Integrators List. This latest achievement enables early development of PCIe 5.0 system-on-chip (SoC) designs, ensuring designers can incorporate the latest high-speed interfaces with confidence that their products will pass compliance testing and reliably interoperate within the entire PCIe ecosystem.
As part of this achievement, Synopsys CXL 2.0 Controller IP is the first such controller to make the Integrator’s List for PCIe 5.0. The main advantage of using the CXL interface, which is based on PCIe 5.0 electrical specifications, is its cache coherency. While PCIe is ideal for applications with large data transfers, CXL is well suited for accelerators, co-processors, and other systems that share data from the same memory space.
Watch this video to see Synopsys CXL 2.0 IP compliance tests and interoperability demo with Teladyne LeCroy Z516 Exerciser.
The Peripheral Component Interconnect Special Interest Group (PCI-SIG) is the body that governs a standardized approach to peripheral component input/output data transfers. Its 800+ company member community specializes in developing interoperable products based on different specifications, including its PCIe framework designed for different applications such as enterprise, desktop, communication, and mobile platforms. The 5.0 version of the PCIe specification increased the data transfer speed and bandwidth capabilities to a maximum link speed of 32 GT/s offering up to 128 GB/s.
Read on to learn about some of the main benefits of PCIe compliance, what the testing process is like, the differences between the 5.0 standard and previous generations of PCIe, and some recommendations to consider when designing solutions with PCIe compliance in mind.
Emerging innovations require higher CPU speeds, faster memories, and high-performance consumer devices, fueling the need for system interconnectivity with greater bandwidth scalability. Industry standards such as the PCIe architecture ensure these requirements are met for varying market segments, whether they’re data centers, artificial intelligence/machine learning, or cloud computing.
In the world of chip design, one of the main concerns is ensuring that all products in the marketplace can work together, and PCI-SIG Compliance Testing helps ensure that. Companies bring their products to PCI-SIG Compliance Workshops to confirm that they meet key aspects of the PCIe specification, and more importantly, that they can interoperate with other products in the ecosystem – whether they are from customers, competitors, or other ecosystem partners.
While internal testing can be done to check this cross-vendor functioning to a certain extent, passing PCIe compliance is a much more effective indication that the products’ interoperability with other vendors has been comprehensively validated by various industry leaders. As the saying goes, “the proof is in the pudding.” When backed by this compliance, developers can build their chips with a high degree of confidence that their devices will work with others in the market.
Passing PCIe 5.0 compliance — or any PCIe standard, for that matter — is no easy feat. The process consists of two distinct testing categories: interoperability and Gold Suite tests. These are carried out at PCI-SIG Compliance Workshops and are the result of numerous development events conducted between PCI-SIG member engineers. The members produce a set of tests and specifications designed to gauge each product’s conformance to key specification parameters and ensure functioning with other devices.
The interoperability tests are part of what many community members refer to as “plugfests.” More akin to physical interoperability testing, this part of the process is where engineers from different companies bring their devices and “plug” them together to directly evaluate how well they can connect. For instance, let’s say Engineer A brings a PCIe 5.0 add-in card he or she designed, and Engineer B brings out their PCIe 5.0 server or desktop. Engineer A brings their add-in card around to the system of Engineer B and the two confirm that the PCIe link is correctly established at the highest common link speed and greatest common link width. Then, they confirm the functional operation of the two devices. The process repeats with Engineer A visiting many other systems, and Engineer B testing several other add-in cards. Participants are generally highly motived to resolve any issues, and it’s not uncommon to see two engineers engaged in a lively discussion and debug session – even if they return to being active competitors after the event ends!
Gold Suite testing, on the other hand, is where parts of the PCIe specification that have been judged as key components for interoperability are tested. These include using a variety of electrical protocol tests and related equipment, such as bit error rate testers to assess the quality of signal transmissions and oscilloscopes to view and analyze devices’ electrical signals. While it’s impossible to verify every parameter and permutation of the PCIe specification at a week-long event, these tests represent the accumulated learnings of several thousand of engineer hours to focus on those that most influence interoperability.
Every industry standard poses its own set of challenges. When designing IP solutions for PCIe, it’s important to continually attend and test out devices throughout the various PCI-SIG compliance workshops held each year. This provides the maximum possible exposure to interoperability testing since different devices are brought to each workshop.
While passing one compliance workshop is sufficient to get on the PCI-SIG Integrators List, continuing to attend and test at multiple workshops is what provides real benefit. It’s arguably even more important to participate in the development events mentioned earlier (often called “FYI workshops” or “pre-FYI workshops”). These help PCI-SIG develop the compliance tests and allow vendors to fortify their product from the very early stages of the design process, ensuring all electrical, transactional, and configuration specs are covered early on. Thus, facilitating compliance once the final deciding workshops come around.
Moreover, in the IP world, we tend to think of PHY and controllers as separate things. However, to pass compliance tests, one needs to work with devices that can be tangibly held and evaluated. What use is having the greatest controller in the world if you cannot hook it up to a PHY so that it can communicate with the outside world? Similarly, a PHY by itself cannot be controlled appropriately to go through all the different components of compliance testing. Vendors who specialize in one or the other typically need to partner with other industry players to ensure end-to-end compliance. Building the two pieces together from the beginning — as Synopsys does — makes a great difference in terms of the thorough understanding and deep skillset needed to achieve successful interoperability and pass extensive compliance testing.
At Synopsys, we actively participate in the PCI-SIG community and the development of these tests by providing our PHY and controller IP solutions to serve as test vehicles from the very first pre-FYI workshop. This means that other vendors can continually test and debug their products with our IP solutions and prepare for final compliance testing well ahead of time. Other ways that Synopsys “puts its money where its mouth is” include sponsoring PCI-SIG Developers Conferences, allowing me time to serve on the Board of Directors, and donating the time of dozens of engineers who actively contribute to multiple PCI-SIG workgroups.
Unlike most vendors testing for PCIe compliance, Synopsys also runs its IP in both add-in cards (Endpoint) and system (Root Port) configurations, providing a broader interoperability perspective within the industry. Since most systems rely on PCIe Root Port designs from a few large CPU vendors that typically utilize proprietary implementations and not open-standard IPs, testing with them as an add-in card (Endpoint) is absolutely essential. However, the only way to test with the wider variety of PCIe Endpoint implementations used in add-in cards is with a system and its associated PCIe Root Port IP. Since most other IP vendors test only as add-in cards, customers of their Root Port IP will have to implement their own system before being able to evaluate interoperability with all those other implementations. Testing our PCIe IP in both configurations gives our customers the peace of mind and confidence that their designs will work with the whole PCIe ecosystem regardless of what PCIe implementation their device connects to.
Working with silicon-proven, vendor-vetted IP is critical for several reasons. It provides a much higher likelihood that your silicon will work on the first pass and will be compatible with that of other vendors. It also limits the number of bugs that could lead to timely and potentially costly silicon design respins down the line while also ensuring data security. Partnering with the right IP vendor can not only help you reap the many rewards of PCIe, but it can also put you ahead of competitors as you gear up for tomorrow’s increased application complexity and speed requirements.
Catch up on other PCI Express-related blog posts: