Our digital world is swimming in data, and the faster the data gets transferred from one point to another, the better performance you’ll see from an array of applications, like the metaverse, with its enriching interactions. Another example is big data analytics that deliver insights on hugely complex dilemmas, such as vaccine discovery, climate change, or financial forecasting.
Making these experiences and discoveries possible is the PCI Express (PCIe) 6.0 specification, which became available last year and doubles the data transfer rate of its predecessor to a blazingly fast 64 GT/s per pin. Faster data transfer means faster computations for applications like high-performance computing (HPC), AI inference engines, and cloud-based software, as well as for solid-state drives (SSDs) used in data centers.
We may not start to see hardware adopting the latest version of the popular I/O bus specification until later this year; however, Synopsys and Keysight have accomplished an important milestone that promises to spur PCIe v6.0 adoption: the industry’s first two-party 64 GT/s linkup. What this signifies is a clean and successful exchange between two ends of a link without any trips to recovery, which are typically caused by aberrations in signal quality. The next step in this journey is to transfer data, such as memory reads and writes, at the PCIe v6.0 data rate of 64GT/s.
SSDs are an early integrator of PCIe v6.0 technology. The bandwidth requirement for SSD SoCs is quite high because these devices interface with both non-volatile memory express (NVMe) and Flash memory as well as root complex processors. While their storage capacity has increased thanks to technology advances like stacked die, SSDs are limited by the bandwidth of the SSD socket, which is in turn gated by the PCIe data rate. The increase to 64 GT/s provided by PCIe v6.0 devices promises to be a boon for SSD SoCs, enabling them to take full advantage of increases in storage capacity.
Overall, PCIe v6.0 technology provides an answer to the bandwidth limitations that compute-intensive SoCs are continually up against. In addition to the faster data transfer rate, the newest specification provides:
The PCIe v6.0 standard is the first version of PCIe technology to use pulse amplitude modulation 4-level (PAM4) signal encoding. PAM4 enables PCIe v6.0 devices to deliver double the throughput of the preceding PCIe spec version with the same channel bandwidth as well as low power and backwards compatibility.
For Synopsys and Keysight, the process of establishing the linkup at L0 involved sending data packets first at a slow speed and negotiating up to the higher speed across the serial link, exchanging equalization information along the way. The links are quite sensitive—even a bumped wire can trigger a trip to recovery and renegotiations. Keysight’s comprehensive portfolio of PCIe testing solutions includes a protocol analyzer that examines traffic moving across the link and an exerciser at the end point for compliance and stress testing. The end-to-end hardware linkup was completed with the Synopsys HAPS®-100 prototyping system, which was connected to a 64G PHY daughtercard connected to a controller to form the complete system.
The PCIe v6.0 specification is complex, with close to 2,000 pages comprehending the BASE spec. When a vendor can demonstrate that it is following the specification correctly, and do so with a third party, this provides confidence of successful interoperability. Synopsys had previously achieved the 64 GT/s linkup with the company’s own hardware. Achieving a rigorous demonstration of a two-party linkup with Keysight, a longtime collaborator, not only validates the interoperability, but this achievement, along with the data transfer rate, is key to enabling applications like data center virtualization and allowing for better utilization of data center resources.
Proven IP is an important part of the equation for successful deployment of a PCIe v6.0 device. Synopsys, which has the most PCI-SIG certifications among IP vendors, offers a complete IP solution for PCIe v6.0 devices. Synopsys IP for PCIe 6.0 includes the controller, PHY, verification, and integrity and data encryption (IDE) security module IP. The IP enables real-time data connectivity with low latency and high throughput for HPC, storage, and AI SoCs.
At this year’s DesignCon high-speed communications and system design conference, Keysight demonstrated the performance of Synopsys PCIe 6.0 IP transmitter and receiver using its UXR 80GHz oscilloscope and M8040A 64GBaud bit error ratio tester (BERT). Keysight offers a full physical layer test solution for PCI Express, comprehending both PCIe v6.0 transmitter testing (BASE) and PCI v6.0 receiver testing (BASE).
As Synopsys and Keysight continue their collaboration, designers developing PCIe v6.0 solutions can look forward to working with trusted vendors for IP and test solutions that can help them realize the promises of this speedy serial communication standard for demanding applications in HPC, AI, and more.
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