From Silicon To Software

 

Addressing Signal and Power Integrity Challenges for High-Speed Data Center Applications

Signal integrity and Power Integrity Analysis
By Pavani Jella, Sr. Staff Product Manager, Synopsys EDA Group

With increasingly larger volumes of data and incessant demands for faster results, chips are being asked to do a lot more these days. Today’s advanced communication systems require that the high-speed data transfer between system components be of very high quality. This helps ensure that data centers responsible for storing and processing big data can generate reliable insights for real-world applications, whether these are over-the-air updates for automotive, natural language processing on the edge for voice-controlled virtual assistants, weather monitoring, or pandemic tracking.

What’s the key to ensuring high data transfer quality? Signal integrity (SI) and power integrity (PI). In this blog post, I’ll take a closer look at the needs of high-speed designs, the role of SI and PI, and three key requirements for an effective SI and PI solution.

Why Is It Getting Harder to Meet Signal Integrity and Power Integrity Demands?

Signal integrity is all about ensuring that the ones and zeros transmitted appear as they should at the receiver end, while power integrity is about having enough current in the drivers and receivers to send and receive the ones and zeros. Keeping the data and power supply clean while minimizing crosstalk, noise, jitter, and inter symbol interference (ISI) helps ensure proper circuit operation.

In high-performance systems, including those based on multi-die architectures, there are interconnects between the package, substrate, PCB, and backplane. All of these need to be assessed for signal and power rail quality; otherwise, there’s the risk of failure. Ideally, any issues should be detected via pre-silicon analysis. Waiting until you’re at the bring-up lab to find SI and PI problems is simply too late in the design project.

However, the combination of today’s faster data rates with more complex protocols are making it harder to comply with SI and PI requirements. Consider DDR memories as an example. As each generation provides increasingly faster data transfers per second, newer and more complex equalization-based measurements have emerged. DDR5, for instance, calls for testing of parameters such as jitter sensitivity, voltage sensitivity, stressed eye tests, and loopback output timing to comply with the standard.

What’s needed to overcome these challenges are smarter, more automated chip design and signal and power integrity analysis tools. For instance, design engineers can use signal and power integrity tools to uncover system design issues earlier in the simulation phase, minimizing the risk of chip defects stemming from SI and PI bugs.

Three Key Requirements for an Effective SI and PI Solution

Signal and power integrity EDA solutions can help ensure that high-speed data is transferred accurately and with integrity. Such solutions are important for chip designers testing high-speed interface I/Os, as well as for PCB engineers evaluating whether a channel on a PCB can transfer data efficiently, with the data intact. Both types of engineers must ensure signal quality while also addressing, during simulation, potential problems that may emerge from signal degradation due to higher data rates. These potential problems could include:

  • Crosstalk and ISI stemming from proximity to adjacent wires
  • Reflection and ring back from impedance mismatch, duty cycle distortion, and jitter induced from nonlinear buffers
  • Imperfect supply, which causes voltage level bounce that, in turn, produces noise and jitter in the system

What’s needed in a signal and power integrity solution to accelerate your time to signal and power integrity compliance? Here are three important requirements to consider as you evaluate your options:

  • The solution should provide a complete, end-to-end SI and PI flow with a silicon-accurate golden simulator for comprehensive analysis; the solution should also extend to the 2.5D and 3D multi-die systems that are becoming increasingly prevalent.
  • The end-to-end flow should include an analysis environment for viewing, probing, and processing large amounts of SI and PI simulation data.

Addressing the challenges of SI and PI compliance for high-speed designs, Synopsys offers tightly integrated solutions from the Synopsys PrimeSim™ circuit simulation family. Synopsys PrimeSim HSPICE® simulator, the industry’s gold standard for accurate circuit simulation, provides co-evaluation of signal and power integrity. It can accurately account for ultra-low bit error rate measurements, which are critical for compliance. The solution can model non-ideal effects like noise and jitter, calculate power supply-induced jitter for timing budgets, capture input data-independent periodic noise from the power supply, and inject a wide variety of jitter. Synopsys PrimeSim SPICE circuit simulator provides a GPU-accelerated high-capacity engine to simulate large-scale systems with post-layout parasitics, enabling efficient final verification at the full transistor level. Integrated with these PrimeSim solutions is the Synopsys PrimeWave™ Design Environment, which provides a flexible, comprehensive environment for simulation setup and analysis.

Learn More at SIPI Special Interest Group Event

An opportunity is coming up for SIPI engineers to learn more about signal and power integrity challenges and solutions. The 2023 Signal & Power Integrity (SIPI) Special Interest Group (SIG) will be meeting from 6:30 p.m. to 9 p.m PST on February 1 at the Hilton Santa Clara. During this forum, attendees will hear from technology experts, learn about customer and partner use cases, and see product demos. For more information on Synopsys SIPI solution, visit our web page: www.synopsys.com/sipi

Ensuring signal and power integrity in today’s high-speed designs can be challenging. But with the right EDA design and analysis tools, the process to comply with the standards and produce a high-performing chip doesn’t have to be so taxing.

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