From Silicon To Software

 

Why 2023 Holds Big Promise for Multi-Die Systems

chiplet technology
By Shekhar Kapoor, Sr. Director of Product Management, Synopsys EDA Group, and Michael Posner, Senior Product Line Group Director, Synopsys Solutions Group

This article was originally published in Electronic Design.

If it seems like everyone’s talking about multi-die systems, you’re not mistaken. The semiconductor industry isn’t only talking about them—multi-die systems are already in the market. With compute demands ballooning and Moore’s law waning, integrating multiple heterogeneous dies, or chiplets, into a system in the same package offers a way to meet aggressive power, performance, area (PPA), cost, and time-to-market requirements. Multi-die systems allow designers to accelerate scaling of system functionality at a cost-effective price, reduce risk, and rapidly create new product variants for flexible portfolio management.

But while the multi-die system train left the station a year or two ago, it has really only been chugging along. Until now. The coming year, 2023, looks to be an inflection point as multi-die systems start to make deeper inroads into the mainstream semiconductor world.

Why do we think 2023 is the year for the seismic shift to multi-die systems? The big change is that the broader ecosystem around these architectures is maturing, providing greater opportunities for cost-effectiveness as well as success. Investments in design and verification tools, IP, and manufacturing are converging to help overcome previous barriers, paving the way for adoption of multi-die systems to ramp up. Read on for more insights into what’s on tap for multi-die systems in the coming year.

Smarter Products Demand Much More from Their Chips

Smartphones that become smarter with each generation. Al algorithms and big data teaming up to generate insights, driving further progress on major challenges from vaccine discovery to climate change. Advanced robotics that can produce goods or perform surgery. The level of intelligence in our devices and systems is growing rapidly, and with this comes far greater demand for more functionality, higher bandwidth, better performance, and lower power—often within the same or smaller footprints.

Moore’s law has been a stalwart since its inception, delivering a doubling of computing performance every couple of years along with overall power reductions. In our current data-driven era, however, performance needs to scale at a much more rapid rate just to keep pace. Processing, memory, bandwidth—they’re all hitting some hard walls with monolithic SoCs. In addition, we’re fast approaching the reticle limits of manufacturing, when density scaling will slow substantially as costs increase.

This is where multi-die systems can shine, providing a new avenue to spark continued innovation.

Multi-die systems—integrated heterogenous chiplets—can boast trillions of transistors, providing the flexibility to designate dies for particular functions to certain process technologies based on their unique requirements as well as overall system performance and cost targets.

Design starts for multi-die systems are anticipated to grow significantly over the next several years, starting in 2023. The biggest adopters of this architecture in the immediate future will likely be those in the high-performance computing (HPC) and hyperscale data center spaces, given their compute-intense workloads. Chip designers in the mobile sector also have multi-die designs in the works, taking advantage of the PPA benefits for their space-constrained devices. Factoring in the many flavors of multi-die, some mobile manufacturers are tapping into advanced packaging to increase chip density. Automotive chip designers are adopting multi-die architectures as well (see the Tesla D1 for AI model training for an example), and we’re seeing increasing interest from more chipmakers in the sector. It’s no wonder—by using different dies for different specialized functions, automotive subsystems can be better positioned to meet overall PPA and cost requirements.

The reality is, multi-die systems are being rolled out across all application segments, given their cost, functional integration, and scaling advantages. So, the question is not whether different sectors will move this way, but when. All signs point to 2023 to be the start of a trajectory toward mass adoption.

Maturing Multi-Die System Ecosystem

The ecosystem around multi-die systems is maturing quickly, and this is critical to enabling wider adoption. While chipmakers such as AMD, Apple, Amazon Web Services, and Intel already have such designs on the market, other key players in the industry are making serious inroads. One big driver is in tool enablement. While proprietary tooling and scripting requiring manual analysis have been prevalent, there are now a broader range of holistic, unified, and mature tools that ease design, verification, testing, signoff, and silicon lifecycle management functions, hiding the deep complexity from users. Standardized IP for robust and secure die-to-die connectivity is now available, too, to lower integration risks and accelerate the chiplet market.

Another sign of the maturing ecosystem is the activity on the foundry side. There are alliances, flows, and advanced packaging technologies available to support multi-die systems. Synopsys is a part of key industry alliances and Synopsys 3DIC Compiler co-design and co-analysis platform is qualified for key flows and production-proven for advanced packaging technologies. Outsourced semiconductor assembly and test (OSAT) providers are other players in the manufacturing supply chain providing the required technology for multi-die packaging.

Indeed, advances in the packaging landscape are contributing to the multi-die growth. Most notably, silicon interposers, redistribution layer (RDL), and 3D-stacked advanced packaging have provided a significant breakthrough, delivering high integration density and improved power efficiency and performance.

On the standards front, the Universal Chiplet Interconnect Express (UCIe) specification is proving to be a key enabler, and is emerging as standard of choice for die-to-die connectivity for various reasons:

  • The specification currently supports 2D, 2.5D, and bridge packages, and support for 3D packages is expected
  • It’s the only standard with a complete stack for the die-to-die interface
  • And it supports bandwidths of up to 32 Gbps per pin—enough for today’s and future applications

Yet another technology that is seeing a lot of development is silicon photonics, which uses the power of light to transmit and process data and is taking hold in heterogeneous multi-die packages. By delivering energy-efficient bandwidth scaling, photonic ICs integrated into multi-die systems provide an answer to address increasing power and data volume challenges. OpenLight, a company formed by Synopsys and Juniper Networks, provides an open silicon photonics platform with integrated lasers that simplifies the process of integrating silicon photonics into a chip design.

From Inflection Point to Take Off

If late 2022 is an inflection point for multi-die systems, 2023 looks to be the year when these architectures really take off. With our comprehensive multi-die solution, including EDA tools and IP, Synopsys enables early architectural exploration, rapid software development and system validation, efficient design implementation, robust die-to-die connectivity, and improved manufacturing and reliability. The Synopsys multi-die system solution includes technologies for die/package co-design, verification, IP, test and repair, signoff analysis, and silicon lifecycle management.

Some design teams may find that a multi-die system approach is simply more cost-effective than moving down another node. Others may want to take advantage of the PPA, cost, and time-to-market benefits. Regardless, multi-die systems are poised to become as mainstream as the monolithic dies inside them, driving higher levels of performance from applications that continue to transform our lives.

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