2022 has proven to be a promising year for the EDA industry. Amidst the historic passing of the CHIPS Act, unveiling new technologies that can be powered by semiconductors, and adapting to new economic conditions, a defining characteristic of the technology space has been the steady increase in systemic and scale complexity. While this has become increasingly challenging for chipmakers, it continues to drive innovation in critical areas such as artificial intelligence (AI), hyperscale data centers, and multi-die systems, resulting in the surge in demand from their underlying chips.
Navigating through such an intricate, complex path is no easy task and requires unwavering support from an ecosystem of customers and partners around the world. As we continue to help our customers extract more from Moore’s law and address changing market dynamics and systemic complexity, we are grateful for their relentless commitment to advancing and helping us discover what the future of possibilities truly holds. We wouldn’t be here without them.
As we wrap up this year, here is a look back at some of the key milestones and themes that defined 2022 at Synopsys.
The right infrastructure is crucial for effective chip design and innovation, and 2022 saw some important advances in the application of cloud technology to support the design process. The migration of chip design to the cloud is not straightforward. But design workloads can vary dramatically, and fixed compute capacity can become a stumbling block. The flexibility to scale up or down is a valuable asset, and designing in the cloud is becoming an increasingly effective way to enable this.
We saw pay-as-you-go SaaS having a transformative effect for cloud-optimized EDA. With this in mind, we launched the industry’s first cloud solution in March: Synopsys Cloud. Built on the Microsoft Azure platform, it gives teams access to cloud-optimized design and verification products while helping to balance the need for complex functionality and energy efficiency. Being able to scale per dynamic chip design and verification needs sounds like a simple step forward. But the FlexEDA model heralds the start of a more designer-friendly world. It allows companies to focus on time to results rather than license constraints; easier EDA software licensing and project scheduling; adoption according to resources; and a streamlined chip design lifecycle that is especially beneficial to startups and small businesses.
Synopsys also launched a cloud startup program which gives startups designing ICs of the future with access to a complete browser-based EDA-as-a-service design environment on Synopsys Cloud with free tools, infrastructure, project management, and CAD. The initiative will be driven in collaboration with the reputed VC firm, Mayfield, to further resource and help guide the next generation of companies.
As we noted in February, AI is revolutionizing chip design. Bringing in intelligence and analytics into tools for higher productivity, we are already seeing software such as Synopsys DSO.ai™ autonomous design system dramatically speed up the typically lengthy chip design processes. The era of autonomous chip design is only just beginning, and we expect AI to help the industry achieve the milestone of 1,000x performance improvement by the end of the decade. AI-enhanced circuit simulation, layout, and hardware, among other solutions, are what will enable us to go beyond the current limits of silicon performance.
Alongside increased performance expectations are opportunities for more compact and responsive internet of things (IoT) devices. In the past, this typically meant compromises in terms of features, but teams are exploring new ways to maximize power efficiency and performance in today’s world of low-power design for IoT. Techniques that designers are employing to achieve this include clock gating, the use of multi-voltage domains, power gating, and register retention (often in combination). We can expect continued investment in design techniques and optimization as IoT advances, with exciting implications for end users.
We also took our own steps to make design smarter and more productive. In June, we expanded our EDA data analytics portfolio with the launch of Synopsys DesignDash, an optimization solution that uses machine learning to surface design insights. Working in tandem with our Digital Design Family and Synopsys DSO.ai system, it provides a real-time, holistic view of all design activities to enable faster and better-informed decisions, as well as more effective collaboration in the SoC development process. We see this being critical as designs become more complex, and will continue to build on our efforts to grow productivity through the application of data, machine learning, and healthy curiosity. And in October, we rolled out Synopsys PrimeClosure, a golden signoff ECO solution that addresses drawn-out design closure and has delivered up to 10x greater design productivity against traditional engineering change order (ECO) flows.
A sure area to watch as we enter 2023 is silicon remastering which, as our Chairman and CEO Aart de Geus has pointed out, is likely to be a central solution to global chip shortages. Remastering means reoptimizing existing chips for different nodes, which AI algorithms have made possible in a remarkably short time frame.
Dazzling, technological breakthroughs are grounded in industry standards, such as high-speed Ethernet and USB. In the most recent example, industry standards in the form of the Universal Chiplet Interconnect Express (UCIe) for die-to-die connectivity in a multi-die system are powering the marketplace for disaggregated dies. As we noted in February, the bodies that create and uphold these standards enable interoperability, security, and, ultimately, progress. We strongly believe that it is in developers’ interests to be active participants in the development of standards.
Toward the end of the year, a collaboration with TSMC saw the launch of the industry’s most comprehensive EDA and IP solutions for multi-die systems for TSMC’s most advanced N7, N5 and N3 process technologies. Built on TSMC 3DFabric™ technologies and its 3Dblox™ standard, it is a comprehensive solution to achieve the power and performance that multi-die systems require to meet intensive computing demands.
With reduced data transport time, the technology reduces the cost of testing and yields more reliable data. In the same month, we also moved to address verification needs across the chip development cycle with the industry’s first unified emulation and prototyping system. The product adds prototyping functionality to the existing ZeBu® EP1 emulation system to offer a single verification hardware system with improved performance and compile time for full debug visibility.
Additionally, lifecycle management received a further upgrade in September with the introduction of an on-chip network that dramatically shortens silicon data access and test time. The innovative streaming fabric technology shortens both silicon data access and test time by up to 80% while enhancing data reliability through accurate power estimation.
In 2022, we launched the industry’s most comprehensive secure interface IP products, helping to protect HPC, IoT, mobile, and automotive SoCs against tampering and physical attacks. Security is not an afterthought but an essential part of SoC development. The broad portfolio of silicon-proven Synopsys Controllers for the most widely used standards are integrated with security features to offer low-risk solutions for optimal security, PPA, and latency.
When summer came, we confirmed certification from TSMC, a silicon foundry partner with whom we’ve had a decades-long collaboration, on flows that will help designers optimize power, performance, area (PPA), and latency for next-generation SoCs used in mobile and high-performance computing applications. The chipmaker certified Synopsys digital and custom design flows for its leading N3E and N4P process technologies. We also announced the availability of our Foundation IP and Interface IP on the TSMC processes, helping customers accelerate SoC development and minimize design risk.
A further move to enhance productivity and design closure included the development of an RF design reference flow and companion design solutions kit (DSK) for advanced-node 5G/6G SoCs on Samsung Foundry’s low-power process.
As SoC complexity continues to increase, failing to do so can mean missing out on an opportunity before it comes to fruition. Synopsys continues to stay active in standards organizations’ work groups to develop IP to support the latest data rates and features, including CXL 3.0 and PCIe 6.0.1.
As we said at the top of this review, collaboration is becoming as important as technology itself. This year, our alliances ranged from becoming part of Intel’s foundry services ecosystem alliance to one with SiMa.ai, designed to ease the path for machine learning applications.
We joined the Intel Foundry Services Accelerator EDA and IP Alliance upon launch in February with a view to help chip designers meet what are often punishing product development goals. In the spirit of staying ahead of industry developments, the move has given us early access to Intel’s process roadmap and design kits among other assets, helping to ensure EDA and IP solutions are optimized accordingly, as well as reducing risk and raising productivity for our customers. Given our long history of working with the US government and the aerospace industry, we also joined the trusted Intel Foundry Services’ (IFS’) USMAG (United States Military, Aerospace and Government) Alliance in November.
On the topic of risk mitigation, in March, Samsung Foundry adopted our advanced voltage-timing signoff solution, one of the fruits of another longstanding partnership with Ansys. The technology guards against potentially costly timing failures to support energy efficient design. And speaking of Samsung, we announced multiple successful test chip tapeouts on digital and custom design tools and flows in October as a result of our collaboration with Samsung Foundry. The joint effort has enabled 3nm process technology for challenging mobile, HPC, and AI designs, offering a 50% reduction in power, 30% performance improvement, and 30% smaller area compared to the earlier Samsung SF5E process.
We also deepened our partnership with Arm to help customers develop next-generation mobile applications by optimizing our design, verification, and IP solutions to deliver maximum performance for the latest Arm Total Compute SoCs. This move, built on more than three decades of already close collaboration, addressed the need for secure and specialized processing for next-generation devices, as well as gaming and VR applications.
Considering the role of machine learning and AI in edge computing, we supported SiMa.ai in developing a machine learning system-on-chip (MLSoC) platform. The innovation uses Synopsys design, verification, IP, and design services solutions, and exemplifies the progress that is achievable when hardware and software pioneers come together.
Recognizing the trend towards application-specific silicon to help address the intensive compute demands of advanced high-performance systems, we collaborated with the pioneers who brought RISC-V to the mainstream, SiFive, to accelerate the design and verification of their custom RISC-V-based SoCs.
In terms of industry sectors, mobility, aerospace, and automotive offered fascinating examples of the application of chip design to realize super-sized visions. In March, we examined the link between cars and smartphones — or how MIPI Protocol IP is helping the automotive industry reinvent itself by enabling sensors and application processors to connect. In May, we collaborated with Analog Devices to help powertrain designers for products such as electric vehicles speed up their processes with precise, multi-domain simulations.
Additionally, we looked at the role of optical design in the space race and space observation, noting that the industries of space exploration and semiconductors have advanced side by side. From the early development of transistors to today’s LiDAR systems, semiconductors are essential components in our quest to derive meaning from the universe.
We also assessed what digital twins technology means for the future of aerospace and government applications as well as for automotive applications. Functionality in any of these areas calls for the prototyping, verification, and monitoring of highly complex electronics systems, which given their sometimes-massive scale would be almost impossible without the aid of digital twin representations of the original. Their application to electronics systems is relatively recent, having begun only within the last five years. We think it is likely that the technology will come to be used as a foundation throughout a system’s life.
Our annual recap would be incomplete without taking stock of our own workplace. As organizations continue to reflect on new working styles, we determined that consolidation into a single campus would position us to best serve both our customers and staff. Starting next year, our growing Bay Area workforce will operate from a single headquarters in Sunnyvale, which we believe will foster even greater agility and collaborative spirit.
As a company helping to write the future, we strive to be a good citizen. We believe strongly that the future should not only be smart, but sustainably so. Our industry is resource-intensive and must make big changes for its own sake as well as for humanity and our planet. We strive to reduce our greenhouse gas emissions. As part of this, we unveiled a 111-megawatt wind farm in Texas.
We are also working with academia to address the shortage of tech talent. Purdue University, for example, is using Synopsys EDA technologies and training materials to support its engineering courses and degree programs, which are vital to fostering tomorrow’s innovators. Other moves to build prospective new semiconductor stars included our ongoing internship program, a hackathon in India, and the launch of the Synopsys Learning Center to make training readily accessible from any physical location.
Part of our mission is to ensure that those innovators come from diverse backgrounds. We were encouraged this year by the presence of five female Synopsys employees in the annual YWCA Golden Gate Silicon Valley Tribute to Women Awards: Sifin Cherupilly Abdulkarim, Radha Bhaman, Aurelia De Colle, Jill Harding, and Vidyullatha Murthy. We would like to take the opportunity to congratulate them again here.
Lastly, we continued to encourage employees at all levels to express their views on the topics they are passionate about. Our previous CFO, Trac Pham, discussed the importance of LGBTQIA+ allyship; Luca Amaru, a principal R&D engineer who received the 2022 Design Automation Conference Under-40 Innovators Award, outlined what he sees as the biggest challenges in logic synthesis, as well as reflecting on his career so far; Radhika Shankar, group director of Customer Success, explained how she balances a rewarding career with an equally fulfilling family and personal life; and Alessandra Costa, SVP of our Customer Success Group, joined a number of young engineers to detail what it takes to thrive in the STEM field.
As we look back over a simultaneously challenging and invigorating year, there is much to be optimistic about. We wish you and your loved ones happy holidays and every success in 2023.
Catch up these insightful blog posts over the holidays: