By Manmeet Walia, Product Marketing Director, Synopsys Solutions Group
Between your home, car, doctor, and workplace—from your online posts to your purchases—data is grist for the mill to make modern life easier. In fact, the demand for data is insatiable. With IoT, analytics, machine learning, and more, data is only getting bigger and more complex. The engines driving it all are semiconductors. To meet new technical requirements, delivering more data at faster speeds and lower power and latency, fundamental SoC design paradigms must change. Moore’s law is sunsetting as we approach the reticle ceiling of manufacturing: It’s simply impossible to fit more transistors onto ever smaller chips. This means that the kinds of performance gains must come through a new era of semiconductor innovation.
Today’s innovations are delivering SoC designs that are larger and more complex than ever, bringing with them inherent integration challenges. This means that standard semiconductor IP blocks used for non-differentiating aspects of your chip design are less plug and play than they used to be. This new friction in the chip design process can cost you resources, time, and money. But what if standalone IP blocks came with a comprehensive IP solution within key applications, easing the integration path from die to board and beyond? What if your semiconductor IP vendor offered more solutions like an ASIC vendor does?
One of the biggest decisions you can make in fabless semiconductor design is whether to go with a Customer Owned Tooling (COT) model or outsource to an ASIC vendor. The COT model can have a DIY cost advantage, but only if the chip volumes are high enough, and this also assumes that you have your own back-end teams and tools, as well as the operations and infrastructure, foundry relationships, and testing capability, to bring your designs to silicon. This can be a problem if you aren’t operating at the scale of the bigger industry players. If not, you’d likely choose an ASIC vendor to handle your chip development and manufacturing for you. While you give up some customizing control, you assume much lower risk. All you need to do is provide the front end of your design to your chosen ASIC vendor and wait for your chips to come back.
How can a similar, application-specific model map to the IP portion of your design? While IP may give you standard functions, the process to integrate these functions into your high-end designs isn’t standard at all. To use IP, you must navigate inconsistencies in your design’s component parts, such as the number of lanes, the clock speeds, the number and types of I/Os, and much more. The differences in variables such as these vary by application.
Having an application-specific, ease-of-use integration model for IP blocks can help you overcome these hurdles. Similar to the ASIC model, IP that encompasses an entire solution for the application can be effective in delivering lower cost and risk, using fewer resources, and improving time to market.
Most applications require different customizations. A good example is a PCI Express® (PCIe®) interface where the power, performance, area, and latency (PPA&L) tradeoff can vary significantly depending on whether the application is high-performance computing (HPC), storage, automotive, mobile, or some other application. If PCIe IP is going inside a server, for instance, it needs high performance to be able to bridge the distance between chips—as much as 12 to 14 inches. In this application, good performance takes precedence over power. This is not the case for a battery-powered mobile device which requires low-power states and can trade-off performance for that end.
Synopsys has built IP that goes beyond the block itself to an entire solution for different application scenarios. These solutions address the needs of the application, whether it differentiates on various features, technical PPA&L, or customer-specific customizations, including metal stacks, pitches, or another unique requirement.
Synopsys is the only IP company that has the scale and the infrastructure to address your needs in this way. We use a five-step approach:
Much like development for an ASIC vendor, the Synopsys IP development process involves a great deal of due diligence: we understand design challenges in a deep way because we replicate large SoC designs in real-world contexts—with full integration exercises—to provide complete solutions to ease your process for advanced designs and enable your success.
We make sure we can place and route our own PHY, PCS, or MAC IP, and close timing at high speeds. We take our IP from the die, to the package substrate, and then to the board to make sure high-speed package escapes work on a minimal number of layers. We mockup a large customer SoC with hundreds of lanes together, and then we go deeper into the SoC to understand the cross talk and the IR drops.
We learn from our own experience and then we transfer that knowledge through a complete set of guidelines. Gone are the days of simply selecting IP and then receiving a .gds file of the function to your FTP site, leaving you on your own to do the hard integration work. Our guidelines tell you how to put the IP blocks together, integrate them into your package, and build your board. We make your design life easier—to get it right sooner—sparing you from an otherwise highly iterative design process.
While we cannot replicate the situation of every customer individually, we learn from our early adopters, using their unique experiences and challenges. As we work with them to ease the design process, we simultaneously build our library, leveraging these experiences and cross-pollinating them into recipes for your success.
Synopsys is ubiquitous in the world of semiconductor design, giving us deep market knowledge in a diverse range of vertical markets, as well as the scale and infrastructure to deliver application-specific solutions. Because we do customizations on standard semiconductor IP in real-world scenarios, we can transfer our knowledge and experience to you in the form of complete IP solutions that will reduce time-to-market, risk, and cost.
To learn more about our IP solutions, contact us.