By Johannes Stahl, Sr. Director, Product Marketing, Synopsys Verification Group, and Dale Donchin, Program Manager, Synopsys Corporate Security Organization
Whether your application is security, edge computing, high-performance data centers, mobile, or any other advanced design, today’s semiconductors are smarter, faster, and more sophisticated than ever. Often built with multi-die components, they are comprised of distinct technologies optimized for specific functions through a web of sophisticated interconnects in a single package.
There is no doubt that advanced semiconductors are catapulting us into a new stratosphere of power, performance, and area (PPA) optimization. But while the benefits far outstrip the generation-to-generation Moore’s law gains of old, advanced SoCs are also introducing a great deal of complexity into the design process, including the convergence of analog and digital domains into single systems. In fact, the verification challenges of integrating analog and digital technologies can leave engineers finding bugs after silicon fabrication, leading to a higher risk of failure, increased costs, and lengthened schedules.
Because of the complexities inherent in advanced silicon design, the Defense Advanced Research Projects Agency (DARPA) invested in new high-performance analog/mixed-signal (AMS) verification methods as part of the Posh Open Source Hardware (POSH) program, which in turn was part of the DARPA Electronics Resurgence Initiative (ERI). POSH challenged key players in academia, the EDA industry, and other leaders in research and the semiconductor engineering space to “develop methodologies, standards, and simulation as well as emulation technologies for the verification and mathematical inspection of analog and digital IP to provide proof of functionality and security…” according to Dr. Sung Kyu Lin, program manager, Microsystems Technology Office at DARPA.
Synopsys was proud to be an integral part of the four-year DARPA POSH program, which ended in June 2022. Specifically, our work in the program has resulted in the world’s first AMS emulation technology for design verification. It’s an advancement that, once commercialized in 2023, will greatly reduce risk in modern design.
The traditional method to test and verify the integrity of an analog circuit design is an open-source simulation framework known as SPICE. Unfortunately, when it comes to mixed-signal designs that integrate digital and analog together, SPICE has been falling well behind in its performance, capacity, and capability targets relative to AMS design requirements. For example, one area where it falls short is pre-silicon validation of DDR memories in a multi-die system. Because of challenges like these, semiconductor design has been ripe for a new verification solution.
By participating in the POSH program, Synopsys aimed to improve high-speed system verification performance. In this, we worked to enable verification of complex technologies, such as USB, DDR, PCIe, SerDes, and more, while also verifying the systems and software that support these technologies, and to do it all pre-silicon. To date, finding and fixing the bugs before committing AMS designs to manufacturing has been very difficult or even impossible to do.
As part of POSH, Synopsys collaborated with leading organizations that have active AMS designs. We worked closely with these organizations by giving them verification solutions and iterating based upon their feedback. Through this process, we ensured we were addressing the right, real-world challenges and delivering significant improvements. An example of such a challenge is DDR PHY calibration, required for high-speed memory deployment. It’s not feasible to perform the verification in simulation since it requires multiple, time-consuming transactions between the PHY and its firmware. While emulation provides sufficient performance to execute the firmware, it requires a PHY model that is capable of emulation. This is now possible due to AMS model emulation support. In fact, one customer design resulted in a 97x performance improvement over simulation.
The competitive players in the EDA industry have expertise in digital design solutions, verifying digital processors and other complex IP in a system. Verification of digital designs is at a much faster speed than analog because there are more verification techniques available, such as emulation, for instance. The application of emulation to analog designs significantly increases verification performance of systems containing both analog and digital content.
Because most systems today use very complex components that are diverse and go beyond the world of digital and into analog, many industry-standard verification solutions won’t support these AMS designs. By enabling the Synopsys ZeBu® emulation and prototyping system to process not only digital circuits but also analog ones, we are the first to create technology that can emulate and verify complex AMS designs, pre-silicon—a major breakthrough.
Here is how we did it:
We started off with an established open-source modeling language called Real Number Modeling (RNM), supporting floating-point signal values and other constructs used in analog design. With this language, you can write a description of what the analog components in your design can do. Because our emulator can support that language—it reads and understands the constructs—it can verify your design with the digital logic and with the software altogether. We call this AMS emulation. It takes our current industry-leading emulation technology and adds on a new RNM capability, incorporating a different analog circuit domain.
In the past, verification was a black box in terms of the analog components in your SoC. Analog circuit behavior previously couldn’t be modelled in emulation; it had to be replaced by a simplified model that didn’t represent its operation with a high degree of fidelity, so there was a chance of error in the final design. The new technology enables a more accurate model, resulting in complete system verification before committing the design to silicon.
Our POSH industry partners used the technology in their multi-die designs, validating everything prior to manufacturing. Before this technology, you would have to either wait for silicon to find the bugs or uncover them in a marginal way through simulations that would increase your timeline substantively, so much so that for the most part, this type of simulation was not done. That is why developing AMS systems have traditionally suffered from much higher risk and greater potential for re-spins. Before AMS emulation, the software, analog circuits, and digital system content were largely verified independently. There wasn’t a practical method to validate that all these design components operated correctly together pre-silicon as they should in-silicon. Thus, bugs were found post-silicon. The benefit of AMS emulation is debug and validation of the entire system: AMS, digital, and software, before commitment to silicon, avoiding detection of anomalies in device validation, characterization, or the field.
The POSH program has advanced the world of AMS design. In the future, you can anticipate widely available commercial products to validate your design pre-silicon. This is only the beginning—capabilities to ease the challenges of AMS design will expand over time. Because our latest emulation technology will scale with the speed of hardware, it won’t just work for today, it will improve over time for a future-proof solution. As a leader in high-quality, silicon-proven semiconductor IP solutions for SoC designs, our IP models, many of which are mixed signal, will be compatible with our AMS emulation technology.
If you’d like to learn more about Synopsys AMS emulation, contact us and subscribe to our Aerospace and Government newsletter.