By Jin Zhang, Product Director, Formal Verification, Synopsys EDA Group
Simulation and formal verification are two key verification strategies used in today’s SoC design and verification flow. With their unique strengths and weaknesses, simulation and formal verification complement each other in finding corner case bugs and ultimately achieving verification closure and signoff.
Simulation and formal verification are usually done by different design verification and formal teams with their own set of signoff goals. These teams typically do not collaborate closely because formal verification and simulation can require different expertise and skillsets. However, there are synergies between simulation and formal that can greatly benefit the overall verification effort and accelerate coverage closure. In this blog, we will examine some of the technology connections between simulation and formal so that verification and formal teams can work together to incorporate both technologies effectively and efficiently to achieve verification signoff.
Achieving coverage closure using simulation alone can be challenging. The time spent in simulation and the number of tests run don’t correlate linearly with the percentage increase in coverage goals accomplished. As shown below, the coverage curve flattens despite increased simulation runs over time. This is usually due to two factors: 1) those coverage goals that are inherently unreachable; 2) those hard-to-hit coverage goals might require manual test creation as constrained random simulation may not hit those coverage targets. At some point, running countless simulation tests doesn’t generate the best ROI nor lead to coverage closure.
Formal verification can address both challenges to accelerate simulation coverage closure in two ways:
While the synergy between simulation and formal does not rely on both technologies coming from the same EDA vendor, there are additional benefits when both solutions share other technology commonality. The industry-standard Synopsys VCS simulator and our innovative Synopsys VC Formal solution share many other valuable connections benefiting end users.
Many Synopsys VCS and VC Formal customers are seeing 40% to 80% savings in verification effort while gaining more confidence in achieving verification signoff. This table shows 10 customer designs and the impact of formal analysis in saving verification effort.
For support in maximizing the benefits of formal technologies, the Synopsys Formal Verification Services team provides experts around the world who can assist with methodology training, verification audit, and a variety of turnkey projects.
With their exhaustive capabilities, formal techniques can go a long way in helping prove chip design correctness. By enhancing your simulation methodology with formal technologies, you can accelerate coverage closure to achieve higher quality designs. The tight integration between the Synopsys VC Formal, Synopsys Verdi, and Synopsys VCS functional verification solutions delivers the speed, capacity, and flexibility to verify today’s complex SoCs and get to the bottom of root causes of design bugs. Better yet, you won’t have to be a formal expert to be productive with these solutions.
Synopsys silicon design and verification solutions share common technologies and consistent design interpretation that provide verification engineers with a seamless user experience, higher performance, and increased productivity. Continued innovation in “value links” across Synopsys products enables companies to efficiently design the next wave of transformative products.
Stay tuned for future blog posts exploring how the connections between Synopsys VC Formal and the other tools in our verification toolbox facilitate fast, high-quality formal signoff.
Gain additional insights on verification by reading these blog posts: