You can never have enough memory for an electronic design, especially if your end product involves artificial intelligence (AI) or machine learning (ML). Large amounts of high-performing memory deliver the real-time (or near real-time) results that systems such as autonomous driving and smart devices require.
In the interest of meeting specific performance, power, and area (PPA) needs for AI, servers, automotive, and the like, the design world is moving toward more customized chips rather than general-purpose memory devices. Given the increasing prevalence of these data-intensive applications, chip designers need to quickly produce derivative designs and variants to satisfy the demands.
How can you meet time-to-market targets while developing increasingly large and complex memory devices that satisfy aggressive PPA goals?
This blog post, adapted from a previously published Semiconductor Engineering article, explains why traditional memory design flows are inadequate to support advanced memory devices. Read on to learn how shifting left, with a big assist from machine learning, can help you accelerate your memory design cycle.
More than ever, memories are being grouped into multi-die designs in 2.5D/3D structures. These types of architectures are rather challenging from design, analysis, and packaging perspectives. Consider the complete memory array. Both the interconnects between the dies as well as the power distribution network (PDN) must be considered while designing the most advanced high-bandwidth memory (HBM) or 3D NAND flash chips to optimize for PPA and silicon reliability.
When it comes to advanced memory devices, traditional memory design and verification techniques are not quite up to the task. Simulating large arrays is time consuming and delays time-to-market because of the excessive turnaround time. When design issues are discovered late in the process, the manual iterative loops needed to resolve the issues cause further delays.
A “shift left” of the memory design and verification process is the only way to address these challenges. Shifting memory design left allows you to perform better analysis earlier, avoid surprises late in the flow, and minimize iterations. By applying this approach, you can also avoid the four key bottlenecks in memory development that impact overall turnaround time and time-to-market: macro cell characterization, block-design optimization, the pre-layout to post-layout simulation gap, and custom layout design.
Let’s take a closer look at each of the four key memory development bottlenecks. Macro cell characterization requires Monte Carlo simulations, which, while significant, have traditionally been a manageable part of the analysis stage for memory designs. Advanced memory designs, however, bring substantial increases in time and resources required to perform exhaustive Monte Carlo simulations, making it an impractical solution. For high sigma characterization and to ensure design robustness, billions of simulation runs are needed. Fortunately, ML can be a saving grace here. By using highly accurate surrogate models of the design, trained to predict high sigma circuit behavior, you can substantially reduce the number of runs required. According to published case studies, this approach can achieve speedups of 100-1000x over traditional methods while delivering accuracy within 1% of golden SPICE results.
What primarily prolongs memory project turnaround time and time-to-market is the need to change the design based on insights from the analysis process. Following a traditional flow, you would make decisions on the topology, choose design parameters such as transistor sizes and R/C values, simulate the design, and examine the output. If the results don’t meet your project’s PPA goals, you’d have to tune the parameters, re-simulate, and re-evaluate the results. This manual iterative loop takes up valuable engineering resources and causes schedule delays.
What if machines and algorithms could automatically optimize the design for you? In recent years, we have seen the emergence of design space optimization as a complete AI-driven workflow in digital design. An AI agent could automatically select device parameters, run simulations, learn from results, and tweak to iteratively converge on the right set of device parameters. With much less manual effort, you could rely on AI-driven design optimization to achieve your design goals orders of magnitude faster.
The gap between pre-layout and post-layout simulations is another major source of iterations that lengthen turnaround time and time-to-market. You aim to pre-fetch the impact of parasitics on design specifications such as timing, power, noise, and stability as accurately as possible before layout to avoid unpleasant surprises when parasitics are extracted from the layout. With traditional flows, unfortunately, these types of surprises are common, resulting in repeated layout and simulation. What’s the answer here? An early parasitic analysis workflow that allows for accurate estimation of net parasitics both for pre-layout and partial-layout designs. Based on published case studies, using an early parasitic analysis workflow to pre-fetch parasitics reduced the gap between pre-layout and post-layout timing for designs from 20-45% down to 0-20%. An emerging technology that shows great promise is the application of ML to further enhance early parasitic analysis workflows by predicting interconnect parasitics.
While speeding the simulation and analysis of memory designs is an important step toward shifting the process left, there’s also an opportunity to reduce the time and effort for the custom layout stage. In memory designs, the same sub-circuit topologies recur frequently. Creating and applying templates that extract placement and routing patterns provides the opportunity to reuse existing layouts created by expert designers. Junior designers can tap into those templates to create new layouts using any device size needed. Not only does this save time, it also allows the junior designers to benefit from the expertise and experience embodied in the original layout. According to published case studies, creating and using templates achieves more than 50% faster layout turnaround time for critical analog circuits in memories and produce more consistent layout quality regardless of the engineers’ experience. ML techniques present a next frontier in layout design, automating analog layout placement and routing and driving further improvements in layout productivity.
To overcome the four main memory design and verification bottlenecks , you can find all of the techniques described within the Synopsys Custom Design Family. In the family, the Synopsys PrimeSim™ continuum of circuit simulation technologies provides ML-driven high sigma Monte Carlo and a unified workflow, eliminating the hassles and inconsistencies inherent in point tool flows. In conjunction with the Synopsys PrimeWave™ Design Environment, the PrimeSim solutions also deliver early parasitic analysis. Finally, the Synopsys Custom Compiler™ design and layout solution includes full support for template-based design reuse.
With every generation of chips, memory design and verification grows more challenging. With Synopsys, you get all the technologies to shift memory design left, with faster turnaround time and time-to-market and the PPA results you need.
Gain more insights into memory designs from these recent blog posts: