By Rob van Blommestein, Product Manager for Synopsys Verdi Debug Solutions
With unrelenting increases in design complexity and shrinking time-to-market windows, the chip verification debug cycle continues to dominate more than 50% of the time spent in verification. At the same time, the number of chip design and verification engineers per project is remaining relatively constant. Artificial intelligence- (AI-) driven debug automation is essential to deliver a much-needed productivity boost to augment engineering resources and address the challenges faced in catching more bugs before tapeout and avoiding costly re-spins.
Looking closer at the RTL design and verification loop, after the latest changes to the RTL are checked in, the regression is run and a list of hundreds or possibly thousands of failing tests come back that need to be debugged. The debug environment needs to be predictive. It should be able to understand the RTL being checked in and which engineering resource is checking in that code (either the design team or the verification team). This way, it can automatically assess where failures are coming from. However, with most debug environments, this is not the case. Most debug solutions induce a manual process of debugging these failures, which can be daunting. The failures are manually categorized and sorted into “bins” based on the type of error reported. The bins are then manually triaged to determine whether the problem(s) reside in the design or the testbench. Root-cause analysis (RCA) is done to try and pinpoint the actual bug triggering the test failure. This manual process is iterative, consumes valuable project time, ties up expensive resources, and is error-prone.
The Synopsys Verdi® Automated Debug System is the industry-leading debug solution. The Verdi system started as a waveform viewer and over many years has evolved into the de facto standard for debug with its best-in-class visualization, behavioral analysis, and automated RCA capabilities. Verdi technology is the unified debug solution across all verification and RTL entry tools. Its Fast Signal Database (FSDB) has helped to standardize verification and analysis solutions across the entire EDA industry.
In 2021, AI technology was incorporated into the Verdi system to further accelerate the debug process. This groundbreaking technology, referred to as Regression Debug Automation (RDA), is an AI-driven chip verification technology that includes the necessary predictive analysis to automate the manual and error-prone process of finding the root cause(s) of failures in the design-under-test (DUT) and testbench. MediaTek, an industry-leading semiconductor company, won the best paper award at the Synopsys User Group (SNUG) event in Southeast Asia, demonstrating a 4x improvement in regression turnaround time leveraging Synopsys Verdi RDA technology.
As Verdi technology continues to evolve, not only will the usage of AI grow, but it will also expand its scope to be aware of all the data that is a part of the verification flow. It is also on a path to become intimately tied to verification management and continuous integration/continuous deployment flows to enable customers to find more bugs, meet project schedules, and achieve first-time-right silicon.
Be sure to stay tuned to this blog for continued exploration of AI-driven debug and verification, with new details and insights into how Verdi technology is enabling worldwide collaboration on the cloud, paving the way for ongoing productivity improvements.
In the meantime, please be sure to check out our on-demand webinar, “AI-Driven Verification: Saving Time with Verdi Regression Debug Automation.”