By Shekhar Kapoor, Sr. Product Line Director, Synopsys EDA Group
It’s inspiring to consider all the technological advances that engineers roll out, year after year. As design teams work on new generations of transformative products, demand for compute remains relentless. To meet these demands, multi-die architectures are emerging as a catalyst, sparking continued innovation and opening up new opportunities in application areas like AI, high-performance computing, and mobile.
In particular, 3DICs — three-dimensional ICs built via the vertical stacking of different chips or wafers in a single package — offer a viable way to extend the power, performance, and area (PPA) benefits of Moore’s law. They deliver more processing capability without requiring an increase in chip area or power. They also support a heterogenous mix-and-match approach to maximize target application-optimized process technologies. In short, modular, multi-chip designs, such as 3DICs, look to be a fundamental enabler of systems that must be more specialized to the tasks they’re expected to run for our increasingly compute-intensive digital world.
At SNUG Silicon Valley 2022, a panel of technical experts from the semiconductor industry explored the promises, challenges, and realities of 3DIC technology. With Sanjay Bali, VP of marketing for the Synopsys Silicon Realization Group, moderating, “3DIC Design: Crossing Over from Buzz to Adoption” featured commentary from:
In this blog post, I’ll share a few highlights of the panel’s discussion. Synopsys users can access this panel as well as other SNUG 2022 sessions on demand.
Leading off the discussion, Swaminathan from AMD explained how chiplets—the dies that make up a multi-die design—can serve as general-purpose CPUs as well as address more specialized purposes. The combination of domain-specific chiplets with higher yields presents a significant value proposition for customers. Success of this modular chip approach depends heavily on packaging technologies that allow the dies to come together and communicate with one another. From 2D to 2.5D and 3D, there are a variety of package types with different types of connectivity, and it’s not a one-size-fits-all proposition. The right choice really depends on the requirements of the application.
3D stacking, said Swaminathan, is the Holy Grail of chiplet architectures. Connectivity via hybrid bonding, such as that introduced via AMD 3D V-Cache™ Technology, provides dramatically higher bandwidth density than anything else currently in the industry. With its 3D V-Cache Technology, AMD implemented a hybrid-bonded 64MB stacked cache for a 7nm x86-64 CPU. 3D stacking allows added capacity while also delivering low latency, and the company’s hybrid bonding technology results in higher interconnect density and better interconnect energy efficiency. “3D cache stacking on CPU cores is just the beginning of our 3D journey,” said Swaminathan. “The 3D stacking technology progression along with other advanced packaging technologies will enable beyond Moore’s law scaling and enable complex heterogenous integration schemes not possible even at monolithic designs by the end of this decade.”
These opportunities do bring to light areas that will require further innovation, from testing to power delivery, system-level integration, and more. “We are truly at a new era of computing as design and innovation must take a step up to compensate for Moore’s law slowing down,” Swaminathan said. “Design and EDA partnerships will be extremely crucial in the next 5 to 10 years to accelerate the path to realize these advanced packaging benefits.”
Intel’s Ranade traced the progression of scaling so far, from the 50th anniversary of the Intel® 4004 4-bit microprocessor, celebrated last year, to today’s chips with more than 100 billion transistors. “By the end of this decade, we should be building products with well over a trillion transistors in the package,” Ranade said. “As technologists and architects, our job is really to figure out what are some of the enabling technologies and methodologies that are needed to enable this future.”
Three key enablers, Ranade highlighted, are a new architectural paradigm for partitioning historically monolithic pieces of silicon into discrete chiplets; new design methodologies to deal with the 10x increase in transistor count, particularly at a higher abstraction level to manage the increasing design complexity; and advanced packaging technologies to connect the various chiplets in innovative and cost-effective ways.
In almost every decade, Ranade noted, there’s been a new paradigm in EDA and design methodologies, with the abstraction level continually raised, in line with increasing chip complexities. “No single company can enable everything that is required to make this happen,” Ranade said. “We need a close collaboration across all the players in the design ecosystem: EDA, IP, foundry, and fabless companies.”
In this new era of silicon everywhere, 5G is driving connectivity in mobile, IoT, automotive and more. In other words, it’s a landscape of diverse applications that require diverse design processes. The 2D design process today is anchored on process technology and system architecture to support more functionality. So, said Bansal of Qualcomm, there’s a lot of opportunity in 3D design to bring more functionality in small form factors with better interconnects, higher performance, and lower power.
In her remarks during the panel, Bansal also discussed the importance of interoperability from the system level to the die level as well as across multiple chiplets. Standardization is very key to enabling interoperability, she said, noting that Qualcomm heavily participates in these processes. To make 3D design mainstream, tools and methodologies for designers need to be simplified and standardized. Partnerships through the ecosystem can support this.
Mitra focused his discussion on 3D nanosystems, which he believes are key to the future, as well as techniques to achieve the next 1,000x improvement in computing performance. Abundant-data applications like AI, machine learning, and augmented reality/virtual reality (AR/VR) are demanding massive amounts of computing, and conventional approaches to deliver this are running out of steam. As a response, Mitra presented the N3XT (Nano-Engineered Computing Systems Technology) 3D MOSAIC (MOnolithic Stacked Assembled IC), where multiple N3XT 3D chips are integrated through a continuum of chip stacking, interposer, and wafer-level integration.
“In spite of significant advances in computing over the past 60 years, the computing that we do today is pretty basic because we have a two-dimensional plane of transistors and some wire interconnects…and you’ve got memory chips sitting very far from the compute chip that causes the memory wall,” he said. “In this notion of N3XT 3D, what we try to achieve is what we call computation immersed in memory. You have multiple layers of very efficient logic, densely interleaved with multiple layers of dense memory. This ultra-dense, three-dimensional integration between these various layers for this fine-grained interleaving of logic and memory layers is the key to achieving 100x to 1,000x energy-delay product benefits.”
Disaggregated dies are a way forward in the face of a slowing Moore’s law, especially with compute demands continuing to grow. Efficiently and cost-effectively designing and developing multi-die designs, such as 3DICs, will certainly take a village, as one of the panelists noted. However, close collaboration among all the players in the semiconductor ecosystem will go a long way in driving success—and adoption—of 3DIC designs.
Catch up on these other posts for more insights on 3DICs: