By Avinash Palepu, Sr. Staff Product Marketing Manager, and Makarand Patil, Sr. Manager, R&D; Synopsys Silicon Realization Group
Chip design teams across multiple market segments are continually setting ambitious goals to deliver advanced and differentiated products to their customers. To realize their aspirations, they’re aggressively pushing the limits of power, performance, and area (PPA) on their advanced node designs.
In this PPA push, the synthesis-to-implementation cycle is a key component. For this part of their chip design cycle, most teams use the Synopsys Digital Design Family, namely the Synopsys Design Compiler or Synopsys Fusion Compiler products. They typically want to take advantage of all the sophisticated functions available, like retiming, multibit banking, advanced data-path optimizations etc., to achieve maximal quality-of-results (QoR). Having a fast, predictable SoC design cycle is a key competitive advantage that our customers strive to achieve to meet their short market windows.
It is also critically important for them to be able to respond quickly to frequent, unexpected, and last-minute register-transfer logic (RTL) functional changes. These changes are typically implemented as functional engineering change orders (ECOs) where RTL is frozen and synthesis and place and route are in the late stages. ECOs are necessary to fix functional verification bugs or to address critical new features to be added.
Compared to a full chip re-spin, ECO is a preferred option because it requires less time and money. Unfortunately, these ECOs tend to come very late in the design cycle and could have a high level of complexity involved—which means the ECO impacts sequentials, state machines, clock reset paths, etc. The need for an automated tool has never been more clear.
Functional ECO is the process of inserting logic directly into the gate-level netlist corresponding to a change that occurs in the RTL. An automated solution that provides this function should be able to compare the affected logic cones between the original and ECO’ed design, identify the most compact set of gates that will represent the change, and generate a patch that can be easily implemented in the original place-and-route netlist.
ECOs have a wide variety of implementations that range from adding or removing logic in a design to more subtle changes such as cleaning up routing for signal integrity. All ECOs are focused on delivering products to market as fast as possible with minimal risk to correctness and schedule. Addressing ECOs can be a time of high stress, long work hours, and uncertainty.
Given the schedule pressures under which the ECO generation process operates, what is of paramount importance is:
Given the aforementioned requirements, let us review the limitations of the existing functional ECO solutions in the market (Figure 1).
The first generation of functional ECO solutions suffer from a fundamental process limitation: they all follow a netlist-driven flow. This means that the ECO creation process can only compare two fully synthesized netlists, the original netlist and the newly synthesized ECO netlist. Even though the ECO can be really captured in a few lines of RTL or a few combinational gates, these solutions force the user to go through a full resynthesis of the ECO’ed partition. If the partition takes days for full synthesis, this can be a very expensive step that the design team cannot afford given the schedule pressure of implementing the ECO.
The second limitation is that many of the tools expect a strict replay of synthesis optimizations in the ECO synthesis step. In other words, these solutions expect the ECO netlist to have exactly the same optimizations as that of the original netlist. This is because, during ECO synthesis, the RTL change which is part of the ECO might prompt the synthesis tool to take a different optimization path. For example, some registers that were constant before may no longer be constant after the ECO. Some banking strategies might be different, and so might some register merging or register duplication steps.
A tool that compares these two netlists with different optimizations may struggle to correctly identify the real differences between the logic cones and, hence, fail to produce a functionally correct and/or optimal patch. This ends up placing an unnecessary restriction on the ECO synthesis step. It also leads to engineers doing a lot of handholding or custom setup in order to get that replay capability into synthesis so that the ECO tool can then line up the two netlists and create the most compact patch.
Afraid of facing such complications late in the ECO cycle, designers typically dial back on synthesis optimizations like ungrouping, sequential optimizations, and inversion push to make the ECO cycle smoother. Essentially, the ECO dominates how teams would like to do their synthesis—a scenario that really should be avoided.
Figure 1. Many of the market’s existing functional ECO solutions have limitations that impact quality and turnaround time.
To recap, many existing automated solutions suffer from the following limitations in the journey from ECO RTL ready to ECO done:
Fortunately, design teams have a choice that delivers first-time-right ECOs, faster and with better quality compared to competitive solutions on the market. Synopsys Formality® ECO functional ECO solution starts the ECO generation process as soon as the ECO RTL is ready. This gives the designer a head start and saves precious time during late-stage ECOs (Figure 2).
Figure 2. The diagram on the left shows the limitations of competitive functional ECO solutions, while the diagram on the right highlights how the Synopsys Formality ECO solution delivers first-time-right ECOs with better quality and faster turnaround time.
The solution takes a revolutionary approach by leveraging both the Synopsys Formality Equivalence Checking technology and in-house compilation technologies from either the Design Compiler or Fusion Compiler solutions.
What happens first is, the Formality ECO solution compares the original and ECO RTL, using its structural analysis capabilities to identify and isolate the regions of change which represent the ECO. Its “find_equivalent_net” capability can traverse beyond module and flop boundaries and localize all the way to the net boundary. This approach helps isolate the minimal set of ECO regions required to capture the change in the ECO RTL.
These regions are then sent to the Design Compiler or Fusion Compiler solutions, which are instructed to perform a “targeted synthesis,” which is essentially an ECO-aware smart compile which synthesizes only the regions of change. There is really no need for the full ECO synthesis to be done. Targeted synthesis accurately zooms in and synthesizes only the regions inside modules affected by the ECO. Moreover, the synthesis is a smart compile performed within the context of the full design constraints. This synthesis supports all the optimizations needed, eliminating any compromise in the QoR. This way, the ECO generation assures functional correctness.
Formality ECO technology has demonstrated the ability to deliver up to 10x faster TAT, up to 5x smaller patches, and support in achieving maximal QoR for designs in a wide range of application areas (Figure 3).
Figure 3. The Synopsys Formality ECO solution delivers an array of advantages for higher quality ECOs.
To learn more about a better way to address ECOs, register and attend our upcoming webinar, “Fast and Accurate Functional ECOs with Synopsys Formality ECO,” taking place at 8a.m. PT on August 16.