Logic Synthesis & Chip Design: Q&A with Luca Amaru, R&D Engineer 

Q: What sparked your interest in technology and an engineering career?

A: When I asked my schoolteachers how calculators work, I got a high-level explanation, but I felt there were still many aspects I wanted to understand better. I finally found the answers I was looking for when studying Electrical Engineering and Computer Science (EECS). I could finally understand how a calculator works from device physics to binary representation and Boolean logic. Since then, I have been fascinated by how many reasoning problems can be formulated in Boolean logic, and especially by how one can design algorithms to efficiently synthesize and prove properties on such logic.

Q: Tell us about your Synopsys career so far.

A: I joined Synopsys right after defending my Ph.D in Computer Science at EPFL (Swiss Federal Institute of Technology Lausanne) in Switzerland in 2015, specializing in logic synthesis and verification. So, Synopsys was really a perfect landing for me!

There are several projects I’ve worked on at Synopsys that I am really proud of, just to name a few: exact delay synthesis, scalable Boolean optimization, satisfiability- (SAT-) based optimization, majority-inverter-graphs for timing, and many more. What is really invigorating is to see how these innovations directly translate into power, performance, and area (PPA) improvements for our customers’ designs.

I do feel a sense of pride knowing that some of my inventions really made a difference in helping to design the best chip for some of the electronics I use every day! I think this is something unique to Synopsys and EDA: how many other industries are out there where one can claim such ubiquitous impact of work innovations to everyday life?

Q: What got you interested in logic synthesis in particular?

A: I first got involved in writing logic synthesis code almost 15 years ago. At the time it was to optimize usage of majority gates in Quantum-dot Cellular Automata (QCA) nanotechnology. Since then, I’ve never stopped being fascinated about synthesis. Logic synthesis has strong ties with both theory of computer science and technology. When working on synthesis, one can easily recognize circuit complexity problems, with deep implications to the famous P versus NP problem, and a moment later deal with physically accurate timing models for advanced technology cells. It is such a fulfilling topic to work on!

Q: What are the key challenges in logic synthesis, especially as chips become larger and more complex?

A: Logic synthesis needs to keep evolving as new designs appear, in terms of size, complexity, and technology. In terms of size, some of the optimizations that were scaling OK a decade ago, and are really key to delivering on PPA, need a fundamental re-thinking today at both the algorithmic and software engineering levels. This is a golden opportunity for innovation in synthesis: often when trying to push scalability to the next level, new ideas come up to generate more PPA benefits.

In terms of complexity, our customers’ designs are not only growing larger but also becoming more sophisticated. Handling a relatively small but complex logic reasoning problem can be equally challenging as solving larger problems. For example, in the SAT-solving community, there are known problems with hundreds of inputs that take more time to solve than some problems with tens of thousands of inputs. Now back to synthesis. AI is clearly a strong driver in the growing complexity of modern designs. On the one hand, AI brings together new architectures and deeper interconnection among computational elements, e.g., neural networks. Synthesis needs to keep up to grab all of the PPA advantages on the table, with good runtime, for these designs. On the other hand, AI enables automatic generation of RTL that can be finally configured by the user. In this context, synthesis is asked to find more opportunities to simplify the design as compared to traditional handwritten RTL, where the designer carefully optimizes each line of RTL code.

As far as technology goes, with CMOS node scaling slowing down, synthesis needs to step up and boost the innovation cycle to compensate. And when dealing with the advanced 3nm/2nm nodes, we need more technology-aware synthesis methodologies to address the challenges seen in such small geometries. Moreover, as post-CMOS alternatives, such as superconducting electronics, are under investigation by industry and academia, new logic synthesis approaches often become essential to permit a fair evaluation on these nanotechnologies – especially when they have different logic abstractions than standard CMOS.

Q: What does being honored with the Under-40 Innovator Award mean to you?

A: The Under-40 Innovator Award is a very prestigious award. Past recipients are exceptional researchers and inspiring leaders in EDA. I am deeply honored and humbled to have been selected to receive it this year.

On top of being a personal honor, I think that receiving this award based on innovations in logic synthesis and logic optimization shows that the field is very much alive and still has lots of exciting research opportunities. I hope this can motivate young researchers in the logic synthesis community to keep innovating!

Q: What do you hope to accomplish next?

A: Regarding R&D, lots of exciting work is happening in order to tackle the challenges in synthesis we discussed before. My team and I are also looking into bringing our latest synthesis methods to the physical design landscape. Moreover, the opportunity to use AI for synthesis is very much in our sight. With the help of our machine learning (ML) experts, we are exploring the possibility to use ML to predict the success of certain types of logic restructuring on a given logic network.