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Accelerating IoT Designs: Designing for Low Power in the Era of Smart Everything

low power IoT SoC design
By Ron Lowman, Strategic Marketing Manager, Synopsys Solutions Group

Most of us have become accustomed to interacting with the ubiquitous technology ecosystem daily (if not hourly). From fitness trackers, smart vacuums, and semi-autonomous vehicles to the smart home devices that wake us up every morning, there’s no denying that the internet of things (IoT) boom has proliferated every aspect of our lives. At the core of this instant, at-our-fingertips connectivity are powerful cloud computing and machine learning techniques that thrive on IoT’s ability to transfer massive amounts of information, through both wired and wireless channels, over the internet or to the datacenter.

A lot of these contextually aware and responsive IoT devices have been around for quite some time, but the practice of communicating with each other and being connected to the cloud has unlocked new potential in recent years. According to IDC, connected devices numbered 22.6 billion in 2019 and are projected to grow to 75 billion by 2025 — a foreseeable trajectory given the 180 zettabytes of data consumption expected by then.

With consumers expecting IoT devices to be increasingly compact and instantaneously responsive, system-on-chip (SoC) design engineers are often required to make tough choices between trading off features such as connectivity, security, personalization, and sensor processing for acceptable battery life.

Comprehensive IP solutions and a constant innovation cycle to develop chips that can handle efficient data processing, thrive in ultra-small form factors, and support multiple wireless connectivity standards are critical for teams to incorporate low-power insights to their designs. Today, design teams are exploring several options that were set aside in past designs to enable as much power efficiency and performance out of a design as possible. That said, we are only starting to understand the potentials of each such technique.

Read on to learn more about the need for low-power design, key design techniques to consider, challenges and opportunities to scale IoT applications, and why pervasive connectivity will drive the next generation of IoT designs.

Designing for a Connected World

The beauty of IoT is that it enables devices to exchange data regardless of the device’s location and be controlled in ways that were not previously imaginable. In the past, physical proximity was a key prerequisite for plugged-in mechanical or electrical devices to functionally cooperate. This distance-dependent connection limited the scope of where and how devices could be controlled. Today, microprocessors with advanced communications capabilities have created larger IoT systems and replaced the barrier of rigid physical systems with a vast array of “edge devices.”

Traditionally, the sole goal of IoT design teams has been associated with lowering cost and not power. While lowering power consumption has always been important, when faced with cost reduction as an overriding priority, designers would be compelled to bypass power reduction techniques in the interest of meeting budget requirements. Today’s vertically aligned system companies, on the other hand, see power reduction as a benefit to total cost of ownership. For them, energy use over time far outweighs the chip costs at a per unit basis, so they prioritizing low power and taking advantage of its combination with high performance and efficient processing rather than just driving down silicon costs — completely changing the power game. In short, the increasing market value for low power consumption, extended battery life, and minimal energy footprint has changed the conversation about power.

Advancements in intelligent technologies like artificial intelligence (AI) give teams the ability to narrow down a specific task and optimize every watt of power.

Multiple AI algorithms and the additional flexibility to handle demands from emerging markets will be needed. This will give system engineers the ability to have much more insight into how chips can be optimized for power and shift the trade-off balance from ultimate flexibility and incredibly low cost to less flexibility and lower power.

The Need for Low-Power Designs

Companies all over the world are pushing for more features and functionality in portable, handheld, and battery-powered gadgets. Improving the battery life by reducing power consumption is a key differentiator for such products and is critical to their end applications.

Essentially, the goal of low-power design is to reduce both dynamic and static components of power consumption as much as possible. Switching and short-circuit power make up dynamic power, whereas static power is comprised of leakage current that flows through the circuit when there is no signal activity. The value of each of these power components is directly related to factors like frequency, peak current, voltage, transition time, leakage current, capacitive load, and switching activity.

Low power design techniques

The higher the voltage value, the more power each component consumes. To attain desired performance while consuming the least amount of power, trade-offs for each of these factors are tested through various low-power techniques and approaches to meet aggressive market demands.

Improving the amount of time it takes for a device to transition from off/sleep state to on/active becomes a critical parameter when it comes to deciding whether plug-in IoT devices need elaborate cooling systems or heat sinks, adding to electricity costs. For example, upgrading ICs in server farms where parallel systems are used can result in significant power and cost savings because of the substantial impact that a single chip being used has on the system.

In the past, the main goal for procurement teams was to find the best ways to lower the cost of silicon and incorporate connectivity — an uphill task to successfully achieve both parameters due to the additional memory and peripherals that are required to support those types of demand.

With the proliferation of AI, we expect that more application-specific tasks will provide opportunities for SoC design teams to optimize for specific design features and components. Unlike the smartphone market, these designs must be attractive to multiple applications to ensure that the volume justifies the investment in the design, making it challenging to lower costs.

Key Low-Power Design Techniques

The underlying silicon inside IoT edge devices fundamentally performs three key features: sensing, processing, and communication. What has caused the industry’s rekindled interest in low-power designs is the increasing market demand for IoT devices to have high performance, long battery life, and mobility.

When designing for low power, there are several techniques that can be employed:

  • Clock gating: Performed during logic synthesis where flip flops with an “enable” input are optimized into a clock gating structure. This technique saves a significant amount of area by reducing the need for several multiplexers and minimizes dynamic power by reducing the overall switching activity.
  • Multi voltage domains: With this technique, the functions of a chip are classified into different voltage domain blocks based on performance features. The underlying design then factors in which area of the chip requires a higher voltage to function, instead of the whole area being classified as high performance. This helps reduce both dynamic and static power consumption.
  • Power gating: Similar to the multi-voltage approach at a chip/system level, functions within an IC are classified into blocks based on their power domain. Power gating effectively shuts off the power completely for a block, resulting in both static and dynamic power savings.
  • Register retention: This approach is often used in combination with the power gating technique. When the block is off, either a subset of the flops or all the flops in the block have their previous values saved and then restored when turned on. This saves power by shortening the time and steps required to restore the block’s original state as well as improves the overall ramp-up time.

In addition to the above and using a combination of them together, there are many more advanced techniques such as process node selection, choosing a custom processor for more efficient capabilities, well biasing, zero-pin retention flops, coupling different pieces of the system, dynamic voltage and frequency scaling (DVFS), and adaptive voltage and frequency scaling (AVFS). For instance, many modern-day processors have blocks that use a lower voltage with power gating and have isolation, retention, and level shifters.

Latest Wireless Connectivity Solutions

Today, system designers have many wireless connectivity protocols to choose from, each providing unique benefits that target different applications.

There are those that are based on low throughput wireless technologies like Bluetooth Low Energy that is seeing increased demand with its added features of reduced power consumption and cost, while maintaining a similar range to the classic Bluetooth version.

IEEE 802.15.4-based protocols like Zigbee and Thread offer low-data rate connectivity over short distances and are clearly gaining momentum, along with other propriety protocols. While different standards may have different governing standards and capabilities to offer, including security, location services, and audio, fundamentally they all support the increasing need for larger bandwidth and more devices to connect to the internet. Newer wireless standards like Wi-Fi 6 that offer more speed and better performance in congested areas are being adopted at record rates in almost every latest SoC design.

With future promises of Wi-Fi 6E and Wi-Fi 7 in the cards, there’s a lot of room for innovation and adoption at higher speeds and bandwidth unlike previously seen, creating new requirements for low power.

Accelerating IoT SoC Design Success with High-Quality IP

There are several options for customers to evaluate ways to maximize throughput, allowing design teams to make trade-offs between power consumption, area, costs, or performance. Everything from processors, compilers, RAMs, foundation IP, to an interface IP has power-down features and different trade-offs that need to be considered based on the end application.

For years, Synopsys has been at the forefront of providing comprehensive IP solutions with Synopsys DesignWare® IP, equipping SoC teams to achieve requirements faster for IoT designs and with significantly less risk. The portfolio includes silicon-proven wired and wireless interface IP, data converters, security IP, low-power embedded memories and logic libraries, energy-efficient processor cores, and integrated IP subsystems.

Our extensive investment in IP quality and comprehensive technical support has also broadened our overall customer market, allowing more customers to adopt tools that best suit their needs. Based on the latest configurations and industry standards, we continue to support the industry’s need for high-speed protocols such as PCIe, USB, and DDR while also enabling the highest levels of security for advanced IoT SoC designs.

Summary

As we witness more advancements in IoT technology and the expanded capabilities of portable devices, the increasing deployment of 5G networks and interest in AI and automation will require teams to invest in improved SoC design techniques, design optimization, and customization tools.

Pervasive connectivity will clearly drive the IoT design roadmap and make a bigger impact on finding effective ways to improve operational efficiencies, energy usage, and overall quality of life in cities around the world. By continuing to prioritize low-power designs and extended battery life for IoT applications, worrying about charging your smart devices daily might just be a thing of the past.

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