By Editorial Team
As innovative technologies drive further demand for more powerful chips, designers must continue to deliver solutions that meet present and future needs. But with rapid advancements in emerging market segments like high-performance computing (HPC), 5G, and AI, they face crucial challenges to achieve greater energy efficiency, faster time-to-market, and power, performance, and area (PPA) requirements. Fortunately, there are several approaches to solve the toughest design challenges, and many of them were on display at this year’s Synopsys Digital Design Technology Symposium.
The virtual event took place on October 5 and brought together Synopsys R&D experts, partners, technologists, and system-on-chip (SoC) designers and managers from around the globe to explore new ideas and forge connections through virtual networking sessions. Numerous topics were covered at the event, such as silicon lifecycle management (SLM), functional safety (FuSa) automation, and advanced nodes in both formal keynotes and breakout sessions. The Symposium also featured keynotes from Synopsys’ Shankar Krishnamoorthy, general manager, Digital Design Group, and Nigel Toon, the co-founder and CEO of Graphcore. In case you missed it, you can watch the full event on-demand.
Read on to learn more about key highlights from their sessions and why a scalable and boundaryless way to accelerate the design process will be critical.
Krishnamoorthy kicked off the Symposium by discussing scaling chip designs with increased complexity and details around how AI, data analytics, and other tools can help designers meet PPA goals. He talked about the progression of Moore’s law and how, even though many semiconductor technologies are advancing, a new approach is needed to bring design up to speed.
“Performance and power are definitely not growing at the same trajectory as before. We need to overcome this, because of the relentless innovation that’s happening in the semiconductor industry, to drive this next level of improvement.” – Shankar Krishnamoorthy, General Manager, Digital Design Group, Synopsys
That challenge needs to be solved, and there is a solution – a “booster pack,” as Krishnamoorthy describes, which increases power and performance by applying domain-specific architectures, 3DIC designs, and AI with a SysMoore era architecture. He also addresses how Synopsys tackles power and performance challenges, and the rising cost of engineering productivity, with a six-vector roadmap.
To learn about these key drivers and more, watch Krishnamoorthy’s full session, Boosting Productivity and Robustness in the SysMoore Era with a Triple-play of Hyperconvergency, Analytics, and AI Innovations.
The application of AI in chip design has garnered quite a lot of buzz of late, and for good reason. Toon’s engaging keynote walked viewers through the progression of AI models, breaking down theoretical misconceptions about the technology and discussing some of the potential use cases for leveraging AI’s immense data analysis functionality. He also presented how the advancement of AI models is outpacing hardware capabilities and the various problems that it causes for chip designers. While there are a few hyperscale companies that can handle exponentially increasing compute, it’s not sustainable — especially not once deployment phases are reached.
“We need to reduce the computational burden associated with AI by removing unnecessary processing. [Legacy] chips carry out calculations on dense blocks of data, but the raw materials of AI computation do not present in this way … Too much data, or over-parameterization, actually makes the models worse … To enable this approach in digital form, we designed the IPU [Intelligence Processing Unit] to have truly fine-grained, parallel processing on a massive scale.” – Nigel Toon, Co-founder & CEO, Graphcore
Watch a snippet of Toon’s keynote below.
Legacy processors have restricted AI innovation, but new-age processors have opened the door to new potential. To learn more, watch Toon’s full presentation, Agents of Change: How New Approaches to Processor Design are Unlocking New Possibilities in AI.
The symposium also featured a variety of seminars led by experts from AMD, Arm, Samsung, MediaTek, GlobalFoundries, and many more. These in-depth sessions were of particular interest to those facing new design challenges driven by rapidly growing and emerging vertical segments for HPC, 5G, mobile, automotive, and AI applications.
For more information on the speaking sessions that covered topics such as energy efficiency, improving system reliability, and multi-die (3DIC) integration, and more, you can access the full on-demand videos here.
Catch up on some previous blog posts around design challenges: