By Ian Land, Senior Director, Synopsys Aerospace & Defense Vertical Solutions
When the Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office (MTO) announced its Electronics Resurgence Initiative (ERI) in 2017, it presented a concerted response to a variety of trends that had emerged in the microelectronics industry. Fast-growing cost and complexity were putting pressure on Moore’s law and traditional approaches to transistor scaling. Global factors, including overseas semiconductor manufacturing and innovation, were limiting U.S. Government access to advanced electronics. And there were growing concerns about electronics security.
Today, the ERI leadership team stands ready to “make a significant investment to create a more specialized, secure, and automated electronics industry that serves the needs of both defense as well as domestic commercial sectors.” Synopsys, a prime contractor for DARPA’s Automatic Implementation of Secure Silicon (AISS) program, is primed to lend our technologies and expertise to these efforts.
Our experts will be on hand at the virtual 2021 ERI Summit & MTO Symposium October 19 to 21 to imagine the future and share some of our progress on DARPA programs so far:
The idea of “democratizing secure silicon” has far-reaching impact for government and business. Hardware attacks, from side-channel attacks to glitching to counterfeiting, continue to increase in frequency and severity. These threats ideally should be addressed across the entire hardware lifecycle, and one way to do it is via an electronic design automation (EDA) flow. The multi-phase AISS program is aimed at promoting hardware security through the automated inclusion of scalable hardware security mechanisms in semiconductor IP and SoCs. Collaborating with Synopsys in these efforts are Arm, Boeing, UltraSoC, the University of Florida Institute for Cyber Security (FICS), Texas A&M University, and the University of California, San Diego. For Synopsys, our role in the AISS program reflects our continued commitment to providing industry awareness, enablement, and leadership for secure silicon throughout the semiconductor lifecycle. We are excited that the AISS team recently completed phase 1 of the program and is now moving on toward further innovation and automation in phase 2.
Our second topic for the ERI Summit is a vision of 3DICs, a hot topic in the electronics industry. Vertical stacking of heterogeneous dies in a 3D package provides an architecture for the fast memory access bandwidth that is in demand for applications like high-performance computing, hyperscale data centers, AI, aerospace, defense, and networking. The architecture also provides a way to get more from Moore’s law, in terms of power, performance, and area (PPA). EDA vendors like Synopsys can help pave the path to a smoother, more efficient 3DIC development process through methodologies like design technology co-optimization and silicon lifecycle management, technologies like die-to-die interface IP and Synopsys 3DIC Compiler, as well as full design and verification flows and design services. With three decades of experience and a first-pass silicon track record, the Synopsys System Design Solutions team can help push 3D chip designs beyond their architectural limits, while keeping aggressive project schedules front and center. Our talk illustrates how 3DIC solutions and services can help reduce design size, weight, power, and cost (SWaP-C)—key areas of concern for aerospace and defense designs.
Synopsys has a long history of collaboration with the U.S. Government and defense industry leaders to promote semiconductor innovation for aerospace and defense applications. To ensure compliance of solutions, we actively participate in key standards organizations and government influencers, including DARPA, the National Defense Industrial Association (NDIA), and the Intelligence Advanced Research Projects Activity (IARPA). As part of the second phase of the ERI, in partnership with Lockheed Martin, Synopsys is participating in the Posh Open Source Hardware (POSH) program for continued innovations in analog/mixed-signal (AMS) verification. In the early phases of the program, the team has produced the industry’s first automated flow for AMS emulation, based on the Synopsys ZeBu® emulation technology. This technology can overcome the limitations of current AMS design verification, not only simulation technology, but also traditional digital-only emulation equipment.
From our work to secure microelectronics designs through their lifecycles to our support of systems-based on microelectronics, Synopsys stands ready to move innovation forward in the face of growing semiconductor challenges. We look forward to sharing more with you at next week’s ERI Summit & MTO Symposium!
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