New Horizons for Chip Design


AI Is Designing AI Chips: What’s Next? Find Out at AI Hardware Summit 2021

AI Hardware Summit 2021

By Editorial Team

When most people think about artificial intelligence (AI), their minds may conjure up images of machines that act on their own, without human intervention. Like robotic arms in automated factories or self-driving cars. But what about the “guts” of those machines—the electronic components that bring them to life…and that make an array of compute-intensive applications possible? Without silicon chips, AI applications aren’t possible. And, as it turns out, without AI, it sure would be difficult to achieve aggressive power, performance, and area (PPA) goals on increasingly complex, advanced-node chips under increasingly tight timelines.

Designing bleeding edge AI chips poses a number of challenges and a much-needed productivity boost is needed to complement the expertise that design engineers bring to the table. You can learn much more about this topic at AI Hardware Summit 2021, where Synopsys will host several talks. As a hybrid event this year, the virtual component for the predominant leadership forum for AI hardware will take place from September 13 to 15, while in-person activities will be on September 14 and 15 at the Computer History Museum in Mountain View, California.

Synopsys Co-Chairman and CEO Aart de Geus is on tap to present the keynote at 9a.m. PDT on September 14. In “Can AI Design AI Chips?” de Geus will highlight new innovations that will empower architects and transform architecture as well as AI.

Additional technical sessions by Synopsys experts include:

  • “From App to Silicon: Personalizing AI Hardware” at 3:45p.m. PDT on September 15. This panel discussion, hosted by Stelios Diamantidis, senior director of AI Solutions at Synopsys, and Karl Freund, founder and principal analyst at Cambrian AI, will delve into the fascinating journey from cloud graphs to silicon. Panelists will also debate the future of application-specific cognitive systems.
  • “How Cerebras Does It: Building the Largest Chip Ever Made, and Delivering Unprecedented Deep Learning Acceleration” at 2p.m. PDT on September 13. This technical workshop will be hosted by Thomas Andersen, VP of Engineering at Synopsys, and Dhiraj Mallick, VP of Engineering and Business Development at Cerebras. Cerebras will discuss the systemic complexity challenges around compute, memory, and bandwidth when designing such a large AI chip and how they overcame these challenges using Synopsys AI design solutions, including DesignWare® IP, verification, digital design, and Silicon Lifecycle Management.
  • “Shift-Left Architecture Design for the Data-Driven Era” at 3:05p.m. PDT on September 13. Tim Kogel, principal engineer for Virtual Prototyping at Synopsys, will present this technical talk, highlighting a flow for early simulation of AI architectures to “shift left” the quantitative analysis by 6 to 12 months.

As a Headline Partner at the AI Hardware Summit, Synopsys is pleased to offer a 10% discount on the registration fee with code SYNOPSYS10. Get yourself primed for the summit by watching our on-demand webinar, “Optimized SoC Hardware for Highly Efficient AI Systems.” Ron Lowman, AI strategic marketing manager at Synopsys, and Kavitha Prasad, VP of Business Development and Systems Applications at, cover:

  • Emerging requirements of next-generation cloud, edge/cloud, and edge-device SoCs and systems
  • Tradeoffs of hardware optimization
  • Driving factors for in developing its low-power SoC for machine-learning at the edge

Get 10% off your AI Hardware Summit registration with the code, SYNOPSYS10

The application of AI in chip design has garnered quite a lot of buzz of late, and for good reason. Solutions like Synopsys™ (Design Space Optimization AI) are helping design engineers create better, faster, and cheaper semiconductors., the industry’s first autonomous AI application for chip design, searches for optimization targets in very large solution spaces of designs, using reinforcement learning to enhance PPA. From the solo engineer who designed a low-power communications CPU with 30% less leakage with results in just one and a half weeks to the solo engineer who designed an automotive SoC with 10% lower power and results in two weeks, the outcomes with are impressive.

Indeed, for those who have not yet done so, now is a fine time to create an AI strategy for chip design. AI can help take the guesswork out of chip design, allowing designers to focus their expertise on product differentiation and other value-added tasks, while the machine takes care of less consequential decisions.

The AI Hardware Summit will provide plenty of opportunities to learn more about, a recipient of a 2020 World Electronics Achievement Award, and many other AI solutions for chip design. See you there!

In Case You Missed It

Catch up on our other recent AI-related blog posts: