From Silicon To Software

 

Why Now Is the Time to Create an AI Strategy for Chip Design

AI chip design flow

By Stelios Diamantidis, Sr. Director, Synopsys AI Solutions, Office of the COO

Artificial intelligence (AI) is touching so many aspects of our everyday lives, from consumer devices to broader applications like drug discovery, climate change modeling, and self-driving cars. One of the advantages that AI brings is its ability to derive actionable insights quickly from massive amounts of data. And that advantage is also providing a productivity boost for chip design.

Has your organization developed its AI strategy for chip design?

Year after year, EDN’s “Mind of the Engineer” study reveals how pressured engineers feel with project workloads, resource constraints, and aggressive time-to-market targets. What if chip designers had a way to focus on value-added product features and other differentiating aspects of their designs, without getting bogged down by more manual, menial tasks?

That’s what AI brings to chip design—the ability to expand the exploration of choices in chip design so that you can work at a certain level of abstraction. Think of AI as an engineer’s assistant. While there is a level of apprehension in our society about machines taking over, using AI in chip design can be a strategy to significantly boost productivity, enhance design performance and energy efficiency, and focus expertise on the most valuable aspects of chip design.

AI Takes the Guesswork Out of Chip Design

Indeed, the use of AI in chip design is garnering quite a lot of attention these days. Forbes recently wrote, “Now, the chip industry itself has reached a stage where AI is aiding in the design of these AI chips, and it is enabling engineering teams of all sizes to compete at the relentless pace required in the semiconductor industry.” It makes sense. Chips are getting larger, especially those for burgeoning applications like AI and high-performance computing and the hyperscale data centers that host them. At 46,225mm2 with 1.2 trillion transistors and 400,000 AI-optimized cores, the Wafer-Scale Engine (WSE) from Cerebras is the biggest chip built so far. Yet, it’s becoming practically unfeasible to grow teams to scales that are needed to take on the increased workload of designing these chips, while still maintaining business sustainability.

So, AI offers a way to scale to meet design and business targets. Consider the task of digital implementation, one of the most complex stages of chip design where a great idea begins to take physical shape. Place-and-route (P&R) tools have done a remarkable job keeping up with the complexity of silicon technologies – determining where to place logic and IP blocks and how to route the traces and interconnects that connect it all. Yet the inputs to P&R constitute a vast search space of potential solutions, spanning functionality (macro-architecture), form (micro-architecture), and fit (silicon technology). Clearly, manually processing and analyzing this data can involve weeks of experimentation, with engineers forced to make complex decisions on the fly. What if AI technology can help shave off a substantial chunk of this time by taking the guesswork and manual effort out of the task? What if, with AI, you could accomplish more with your existing team?

P&R is just one example where AI can play a role. Given the increasing complexity of designs, with the vast number of iterations, corners, etc. involved, there are opportunities to optimize many other areas in the process.

Achieving PPA Targets Faster

One disruptive application of AI in chip design is design space optimization (DSO), a generative optimization paradigm that uses reinforcement-learning technology to autonomously search design spaces for optimal solutions. By applying AI to chip design workflows, DSO facilitates a massive scaling in the exploration of choices while also automating a large volume of less consequential decisions. The approach creates an opportunity for the technology to continuously build on its training data and apply what it has learned to, ultimately, accelerate tapeouts and achieve power, performance, and area (PPA) targets. And one of the key advantages of AI is its support of reuse: the retained learnings gained for one project can be utilized for future projects, bringing greater efficiency into the design process.

Freeing Engineering Expertise for Value-Added Work

Last spring, Synopsys launched the first autonomous AI application for chip design, DSO.ai™. Inspired by DeepMind’s AlphaZero, which mastered games like chess and Go, DSO.ai enables AI-driven design space optimization. Analyzing large data streams generated by design tools to make optimization decisions, DSO.ai learns in real time and provides a more robust result in less time than it would take a team of engineers. In this way, DSO.ai seeks optimal PPA targets with less engineering effort while staying within compute and licensing budgets. This frees engineers to focus on more value-added chip design tasks, such as higher yield design spaces. Learnings gained from one project are retained and can be used for future efforts.

DSO.ai, which was honored with a 2020 World Electronics Achievement Award for “Innovative Product of the Year,” provides:

  • A reinforcement-learning engine that can explore trillions of design recipes
  • The ability to simultaneously pursue many complex objectives, formulated in the performance space of chip design (PPA)
  • Full integration with the Synopsys Fusion Design Platform™, which includes RTL design and synthesis, physical implementation, physical verification, signoff, test automation, flow automation, and multi-die system design and integration tools for full-flow quality-of-results (QoR) and time-to-results (TTR)
  • Cloud readiness for fast deployment in on-premises, public, and hybrid clouds

AI soc design flow

In the year that it’s been available, DSO.ai has been integrated into the production flow for several top-tier chip design companies. After adopting DSO.ai in its advanced automotive chip design environment, Renesas has experienced the solution’s ability to autonomously converge to PPA targets and enhance overall design team productivity. In a recent production tapeout, a North American integrated device manufacturer was able to achieve  up to 15% better total power, 30% better leakage, and 2 to 5x faster convergence using DSO.ai – all with a single engineer, in just weeks. An Asia-Pacific global electronics powerhouse was able to identify PPA solutions that were simply deemed ‘unattainable’ with traditional techniques, meeting timing constraints weeks ahead of schedule and boosting maximum frequency by hundreds of MHz. (Learn more by watching our SNUG World 2021 executive panel, “How Is AI Changing the Way We Approach Chip Design?” You’ll need to log in to access the session on demand.)

As Synopsys continues to advance the capabilities of DSO.ai, we are expanding the solution’s ability to identify results faster and with significantly less effort. We are addressing many opportunities to integrate the solution with additional design tools. And we are exploring new and exciting applications of the technology.

How Can You Enhance Chip Design with AI?

When we introduced DSO.ai in 2020, we presented the semiconductor industry with a challenge: what can you do with AI? So far, the industry has responded positively, validating the value of using AI to enhance chip design.

Looking ahead, we see AI moving into the mainstream, as more chip designers recognize the productivity boost this technology can provide in an environment of aggressive PPA and time-to-market targets.

AI is proving to offer impactful and sustainable advantages to adopters. The next question we can explore together is – what is your organization’s AI strategy for chip design?

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