From Silicon To Software

 

The Importance of Chip Manufacturing & Test Data Analytics in the Semiconductor Industry

Chip data analytics

By Guy Cortez, Staff Product Marketing Manager for Silicon Lifecycle Management, Synopsys Digital Design Group

The process of designing, manufacturing, and testing integrated circuits (IC) is complex, extensive, and expensive, especially as IC designs themselves become larger and more complex.

The amount of data that the chip manufacturing and test process produces is massive and overwhelming to the point of being rendered useless unless there is an efficient way to collect and analyze it. As with other data-intensive processes, proper big data analytics tools are needed to help product engineers gather the data, align it, sort it, make sense of it, and provide meaningful and actionable insights to identify root cause of issues and propose corrective actions to solutions.

Timely access to the chip data is critical in managing the key success factors of the semiconductor industry: product quality and yield, operational efficiency, and time-to-market. Read on to learn about the kinds of data engineers are leveraging, the limitations of current tools in the market, and the new Synopsys data analytics solution supporting the semiconductor industry.

A Tsunami of Chip Manufacturing and Testing Data

In a standard manufacturing process, chips are put through rigorous manufacturing and testing stages. Each stage of the process has the potential to unearth valuable information that could prevent any compromised chip from going through the entire process. Detecting issues early not only saves money in the manufacturing and test process but it also helps prevent faulty products from being shipped to a customer and potentially causing a catastrophic failure while in use.

One of the first phases in manufacturing testing, wafer acceptance testing (WAT), occurs after the wafers are produced at the foundry followed by bump testing. In the bump test phase, solder spheres (bumps) are attached to the chip I/O pads while at the foundry. Following that is wafer sort (WS), assembly (ASSY), final test (FT), and system-level test (SLT).

Chip design testing process

The WS phase is the testing that’s typically done by an outsourced semiconductor assembly and test (OSAT) supplier, a third-party company that is in charge of applying parametric tests given by fabless companies (chip developer) onto the wafers while on a tester. In this stage, there can be thousands of tests that are run depending on how elaborate the testing is. The wafer is then diced into individual chips and placed into packages during the ASSY phase. FT and SLT can consist of many of the same tests that were performed during WS but often consists of additional tests as well.

Historically, WAT, WS, and FT were the most common sources of data actively sought by fabless companies for analysis primarily because those were the data sources that data analytics solutions focused on or knew how to handle. This is somewhat still true today. However, BUMP, ASSY, and SLT data are quite important in knowing the full history of the chip and can be invaluable when uncovering issues previously masked by not analyzing this data. A good data analytics solution should be able to gather and analyze all data from each of these predominant test phases.

A simple rule of thumb is the later in the manufacturing process that chips fail testing, the more costly it is due to the wasted tester time spent through the earlier test phases, the expensive packaging now going to waste and, ultimately, the lost revenue of not being able to sell those failed chips. Identifying faulty chips as early as possible, therefore, becomes critical to the financial health of companies developing chips. This can only be achieved with access and visibility to all of the data.

Chip Data Management and the Need for Traceability

When an issue surfaces during any of these test phases, it is paramount that engineers are able to trace back to the root cause to determine if the problem is specific to only a certain wafer or across every wafer manufactured during a certain period of time.

The process of tracing back to see if there is a test parameter or fab process condition from an earlier stage in the manufacturing process that can predict failures encountered during later stages (e.g. ASSY, FT, or SLT) is called data feed backward. To properly perform this traceability, the tool needs to be able to correlate against every test ever run on every chip. This requires the chip to contain an embedded chip ID (ECID).

Aligning data is also important. This is the process of tracking which wafer each die came from and which lot that wafer came from; typically, there are 25 wafers in one lot. Finally, normalizing the data before analysis is required when the tests are conducted in different units (think volts vs. millivolts).

Engineers spend 80% of their time conducting data management (e.g., searching, aligning, normalizing, and filtering datasets) while only 10% to 20% of that data is ever used. There needs to be a more efficient and productive way.

Introducing the Next-Generation Chip Analytics Solution: SiliconDash

To significantly reduce that time preparing the mountains of data available (not to mention analyzing and drawing meaningful conclusions), engineers need big data tools to assist them. That’s where SiliconDash comes in.

SiliconDash is a high-volume, semiconductor chip data analytics solution for fabless companies, IDMs, OSATs, and foundries. It delivers comprehensive, end-to-end, real-time intelligence and control of manufacturing and test operations of IC and multi-chip module (MCM) products for executives, managers, product engineers, test engineers, quality engineers, sustaining engineers, device engineers, yield engineers, and test operators.

Chip design engineering

SiliconDash can be used to improve yield management, quality management, and throughput management. Users are presented with standard dashboards containing automatic results found by the tool. Users can also easily create their own custom dashboards such as corporate traffic light dashboards, supplier dashboards, equipment dashboards, technology dashboards, etc., that map to their own standards for yield and quality.

In addition, near real-time systematic and fully automated data preparation and analytics are provided on all incoming data of the entire manufacturing chain from high-volume data streams across geographically dispersed manufacturing and test operations.

It’s All About the Data Insights and Corrective Actions

SiliconDash uses robust algorithms to analyze the chip data in near real-time. These analytics can be found in dashboards and reports known as “Insights,” which are automatically generated and made available instantly out-of-the-box.

These Insights are completely automated and require no user setup, configuration, or training – an industry first. They highlight key points of interest and enable you to analyze quickly, triage, and identify root causes of issues within minutes.

Let’s say there’s an issue with a probe card on the OSAT test floor. SiliconDash would identify this issue and automatically generate an email to a specific engineer on the product line that specifies the particular tester where this particular probe card resides and is causing poor yield. This allows the engineer to investigate and stop that tester, if necessary, or temporarily disable that probe card while continuing the manufacturing test process. Alternatively, if SiliconDash has been granted access to the Manufacturing Execution System (MES), it could shut down that tester automatically for critical applications until the problem is remedied.

SiliconDash provides over 40 Insights right out of the box; the chart below shows five of the more popular Insights. For instance, the Distribution Tails chart shows how many dies are failing the lower test limit and affecting the overall yield. Users can do real-time simulation to determine how much more yield could be gained by simply clicking and dragging the lower test limit to the left.

IC design tools

The WAT-WS Correlation chart emulates the power of traceability within SiliconDash using correlation as discussed earlier, allowing engineers to detect upstream parameters that can predict downstream issues such as chips failing at FT, for example. By detecting these problems earlier during WAT or WS test phases, there’s a huge cost savings and productivity gain. Productivity is achieved not only in quickly reducing engineering debug time to find the source of the problem but also in enabling overall improved production ramp time of the product as problems are quickly identified and solved.

Synopsys customer Marvell Technology, Inc. recently implemented SiliconDash in their manufacturing testing process and had over 100 users in the first quarter of use. Marvell experienced the following benefits:

Chip data management

Ultimately, end users should factor in how fast and precise data analytics solutions are in identifying and solving problems when evaluating different tools on the market. SiliconDash is the only solution in the market that provides comprehensive Insights of key points of interests and issues found without requiring engineer intervention: no special sorting, querying, or manual manipulation of datasets. Lastly, the ability to receive and analyze test data immediately from all the various manufacturing test stages as well as the ability to cross-analyze and correlate that data to provide correction actions back into the manufacturing chain is also key.

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