By Umang Doshi, Senior Staff Product Marketing and Business Development Manager, Digital Design Group, Synopsys
The artificial intelligence (AI), automotive, internet of things (IoT), and mobile industries have seen significant progress in the last few decades, powered by advanced nodes (think 10nm and under) that are designed using digital technology tools dependent on accurate libraries that map to the latest process technologies.
Designers and foundries use high-quality libraries, the building blocks for system-on-chip (SoC) designs, to decrease time to market and ensure optimal implementation and manufacturability. These technology libraries become increasingly complex as the advanced nodes scale and there is a need for more accuracy for the process, voltage, and temperature (PVT) conditions. Usually, library characterization takes months and with each advanced node, the challenges grow to include a tripling of PVT corners, variation modeling, reliability, and aging effects.
If signoff libraries for advanced process nodes are not available in a timely manner, this can translate to a massive bottleneck for chip designers, potentially delaying project schedules and, consequently, the latest and greatest mobile device, IoT gadget, advancement in autonomous driving technology, etc.
In addition, the smaller the geometry of an SoC is, the lower the margin for error. Accurate modeling is key for advanced nodes. For instance, in variation modeling, the objective is to model how the device will behave when there is a slight change in PVT. A small variation in advanced nodes may be the difference between a working device and an inoperable one.
That’s why Synopsys announced PrimeLib today at our SNUG® World international user conference. PrimeLib is a high-performance, comprehensive characterization and validation solution that produces signoff-quality libraries targeted for SoC design at advanced process nodes. It’s a key enabler for correct-by-construction design as we scale into unprecedented levels of complexity and deal with new manufacturing challenges.
Part of our design analysis and verification solution portfolio, PrimeLib includes SmartScaling for multi-process, voltage, and temperature, advanced machine learning (ML), and integrated validation technologies. It delivers the highest level of validation for golden signoff-quality libraries, with an overall 4x improvement in turnaround time compared to previous generation offerings.
Key highlights of PrimeLib include:
As with most chip design technologies, it takes an ecosystem to realize the potential. By leveraging PrimeLib capabilities with companies like Arm and AWS, we’re helping our customers meet the increased challenges of advanced nodes, thanks in part to a cloud-based use model:
“The demand for library characterization cycles continues to multiply with each advanced node, requiring more process corners and new modeling requirements for variation, aging and reliability, all within a shrinking time-to-market window,” Philippe Moyer, vice president of Design Enablement, Physical Design Group, Arm, noted in the news release unveiling PrimeLib. “Partnering with Synopsys, we have been able to meet these massive compute demands through a combination of Arm-based AWS Graviton 2 processors and Synopsys PrimeLib to provide a cost-effective, linear scaling solution which accelerates throughput for library characterization, reducing turnaround time from weeks to days.”
We briefly mentioned the concept of SmartScaling above, but what does this mean when it comes to library characterization?
SmartScaling is a new methodology built on top of the PrimeTime engine that uses advanced machine-learning algorithms to reduce the actual simulation runtime by using existing characterized libraries as anchor PVT corners to generate multiple additional PVTs instantly. This mitigates the many challenges library teams face as they characterize the large number of PVT corners that come with advanced nodes such as high simulation turnaround time, database disk space limits, license server overloads, and hardware costs.
SmartScaling provides signoff accuracy for various library views (NLDM, NLPM, CCST, CCSN, and LVF) and can reduce library characterization runtime by 3x to 10x and reduce library size by up to 10x (compared to tools without this capability), while also ensuring library accuracy.
Ultimately, today’s designers are under immense pressure to maximize power-performance-area (PPA) under tight project schedules and low margins for error. Having access to a unified library characterization and validation solution like PrimeLib can help designers reduce time to market, ensure PrimeTime signoff-quality libraries with maximum throughput, and make the best use of available compute resources.