By Johannes Stahl, Sr. Director, Product Marketing, Verification Group
The larger and more complex silicon chips become, the more important it is to find and fix problems early in your design cycle—before the issues become more costly and challenging to resolve. After all, no one wants to deal with an SoC re-spin. Thanks to FPGA-based prototyping, pre-silicon software development and system validation have become integral parts of the design cycle.
Prototyping systems, however, are under relentless pressure to do more as chips continue to evolve. Burgeoning applications like high-performance computing, artificial intelligence (AI), 5G, networking, and storage, as well as in-demand key IP like graphic processing units (GPUs), central processing units (CPUs), and AI accelerators, are driving greater silicon complexity and advancements like 3D packaging. Performance and flexibility remain critical for prototyping systems, and they are also increasingly challenging to achieve for larger, more complex chips. In this blog post, I’ll discuss the evolution of FPGA-based prototyping and highlight how the technology has advanced to support today’s SoCs.
There have been three major waves of prototyping innovation. In the first wave, we saw the evolution of build-your-own (BYO) projects based on a single FPGA to commercial boards with multiple FPGAs, the latter paired with generic prototyping software for different types of FPGA prototype boards. In the second wave, prototypes grew larger, involving many boards, and the prototyping software had to support automated partitioning for these much larger designs. New use cases, such as power validation, emerged during this time. And debug tools needed to do more. By the close of this second wave, integrated hardware/software prototyping solutions were the best-suited tools to address the demands of the chips.
We are now in the third wave of prototyping innovation, where the primary prototyping deployment is in server racks in datacenters. This so-called prototyping farm deployment paves the way for multiple, distributed teams to engage remotely in software development, testing, and system validation. Since it’s not uncommon for chip design teams to be spread across different regions of the world, having a seamless way for designers as well as software developers and verification engineers to collaborate from wherever they are helps to maximize productivity. Traditional desktop prototyping remains valuable for use cases like protocol IP validation and is ideally supported by the same prototyping system.
There are two key problems for prototyping to solve:
With every prototyping generation, there’s higher complexity for the prototyping system to support, as well as higher performance to deliver. As the FPGA complexity on a prototyping system grows, we can put more of the design on it. Moreover, our ability to scale, putting multiple prototyping systems together, grows more with every generation. Also beneficial here is the efficiency of a direct connection architecture, where the cables and connectors are implemented to fully and flexibly connect FPGAs to one another on a board and also to connect different boards in a prototyping system. Mapping the communications efficiently on the cables, via sophisticated software, is important here, as is effective system partitioning to drive higher performance.
To meet the verification demands of complex, bleeding-edge SoCs, Synopsys recently unveiled its HAPS®-100 prototyping system. This highly scalable system, pictured below, features a flexible direct connect architecture for highest performance and also leverages an expansive prototyping ecosystem as well as a broad portfolio of HAPS interface cards. The associated prototyping software builds on 20 years of Synopsys experience in FPGA synthesis and delivers high performance using timing optimization for the direct connect architecture.
HAPS-100 delivers benefits in prototyping and debug performance for software and hardware verification of complex SoCs.
With HAPS-100, users benefit from:
Representing the third wave of prototyping innovation, HAPS-100 accelerates software development, system validation, and verification. With HAPS Gateway software, distributed users can work from anywhere for maximum productivity and cost efficiency. The HAPS-100 system is part of the Synopsys Verification Continuum® Platform, which is aimed at shaving months off project schedules by providing the tools for finding SoC bugs earlier and faster, bringing up software earlier, and validating entire systems. The Verification Continuum Platform includes the new ZeBu® Empower emulation system, which provides actionable power verification results on billion-gate designs in hours, and verification IP that accelerates runtime, debug, and coverage closure for SoC designs.
The prototyping landscape is dotted with solutions that have less flexible hardware architectures and that also lack the proven advanced software stack that HAPS-100 comes with. As a result, these solutions are not living up to the performance expectations and requirements of prototyping users.
When it comes to prototyping, every customer is quite unique in how they use the platforms. Much of this depends on their prototyping expertise, as well as their chip design requirements. With every generation of HAPS, we’ve seen customers push HAPS prototyping technology to the limits, doing more with the solution than we imagined.
What’s next in the world of prototyping? We’re just at the beginning of this third wave of prototyping innovation. We expect chip designers, software developers, and verification engineers will continue to stretch the boundaries of our tools as they innovate to meet the exacting demands of applications like AI, 5G, and high-performance computing.
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