By Shekhar Kapoor, Product Marketing Director, and Kenneth Larsen, Product Marketing Director, Digital Design Group
While Moore’s Law may not be delivering the same predictable gains that it once was, new techniques and technologies have emerged to extend design scale despite the ever-expanding challenges posed by ever-shrinking geometries. 3DICs are one example, delivering at once performance, power, and footprint benefits through the vertical stacking of silicon wafers or dies into a singly packaged device.
3DICs, and their close, older brethren 2.5D ICs, are together triggering significant disruption in numerous key application spaces, including artificial intelligence (AI), 5G infrastructure, data centers, large networking systems, and high-performance computing (HPC), to name but a few. What links these seemingly disparate applications is that their die sizes are growing significantly and, thus, present increasing business challenges in managing their associated cost and yield. At a certain retically challenged point, a single silicon die simply cannot physically accommodate all of the logic, memory, and IO needed for these compute-intensive applications.
When it comes to generating the highest performance at the lowest achievable power, 3D architectures are by far the more optimal solution. 3DICs are naturally suited to support compute-intensive workloads by allowing extreme, heterogeneous, and homogeneous integration that provides for the densification and scalability that 2D architectures lack. More recently, even mobile applications, driven by demands for greater performance in a highly constrained form factor, are also tapping into 3DICs.
Indeed, 3DICs are poised to become even more widespread as chip designers strive to achieve the optimum PPA per cubic millimeter. In this blog post, we’ll look at how we can address the 3DIC design challenge.
Transitioning from 2D to 3D IC architectures is not as simple as creating multiple systems-on-chips (SoCs) and blindly stacking them together. In the 2DIC world, designers are accustomed to developing SoCs using an established and familiar set of methodologies, tools, and flows. Moving to 3DICs, they want similar methodologies and flows to be available for their design and validation processes. This mindset has led designers to create their 2.5D and 3DIC designs in a highly fragmented environment that is marked by a swathe of point-tool solutions and myriad ways to (inefficiently) connect them. Consider the “simpler” end of the spectrum in that of a 2.5D silicon-interposer-based, multi-die design. To date, designers have been forced to perform highly manual assessments to determine how to place their IP on each die and where to best place associated micro bumps and through-silicon vias (TSVs) to create the most optimal system-integration architecture. By lacking any integrated analysis and feedback, this task is both cumbersome and error-prone. With 3DICs scaling to hundreds of millions (or more) possible connections, you can see that this approach quickly becomes impractical, inefficient, and, more importantly, very hit and miss. And this is just for one aspect of the overall design flow. In short, jumping around between different tools for design exploration, design implementation, and signoff analysis is not a scalable way to operate for these increasingly complex designs.
Transitioning from 2D to 3D IC architectures is not as simple as creating multiple SoCs and blindly stacking them together.
Another consideration is the workflow efficiency and efficacy among the different teams involved in the overall design process: architecture, design, implementation, IP creation/integration, packaging, etc. For example, traditionally – in the 2DIC world – it’s a relatively simple step of passing the completed chip-level design to the packaging team. However, with 3DICs, this stage entails much more back and forth because the resulting design may not meet the much more exacting packaging requirements.
This back and forth between teams is in large part due to how the system-level optimization happens. In both the 2D and 3D IC cases, ultimately, it’s up to the chip designer to extract the design’s maximum performance at the architectural level. Now, while the level of abstraction for a traditional 2D SoC has evolved from the transistor to the IP level, with 3DICs the level of abstraction is at the chiplet level. Optimizing the design of chiplets to meet performance targets is far more challenging, especially given that these chiplets could be on different process nodes and support various functions. A complete system might include low-power-memory IP, SerDes blocks, computing matrix, and other components, and, of course, everything must work well together once stacked.
Packaging decisions should, therefore, be made based on the performance targets for the system as a whole and with consideration of factors like boundaries and connections when the dies are ultimately stacked. Maybe 2.5D packaging is ideal, or 3D, or a hybrid. As should be evident, there is a significant opportunity to smooth out the workflow between the different teams for greater productivity and quality of results.
The 3DIC architecture also highlights new technical challenges in areas like thermal management and testing. On the thermal side, the TSVs used to connect the dies can lead to poor lateral heat distribution and more heat dissipation, both of which can hamper system performance if not properly managed. From a test perspective, since testing tools can only access the bottom die, a design-for-test approach is needed to identify trouble spots along the entire stack.
The various point tools available only address sub-sections of the complex challenges in designing 3DICs, creating large design feedback loops that don’t allow for convergence to an optimal solution in a timely manner. In a multi-die environment, the full system must be analyzed and optimized together. It isn’t enough to perform power and thermal analysis of the individual die in isolation. A more effective and efficient solution here would be a unified platform that integrates system-level signal, power, and thermal analysis into a single, tightly coupled solution.
Synopsys offers such a unified platform for multi-die integration via 3DIC Compiler, which provides a single, hyperconvergent environment for 3D visualization, pathfinding, exploration, design, implementation, validation, and signoff. The platform is built atop the Synopsys Fusion Design Platform‘s common, highly scalable data model. As such, the platform enables efficiency while also scaling in capacity and performance, supporting billions of inter-die interconnects. It also reduces the number of iterations through its full set of automated features while providing power integrity, thermal, and noise-aware optimization. Synopsys has partnered with Ansys, with 3DIC Compiler providing in-design support of the Ansys® chip-package co-simulation tools for a comprehensive analysis of signal and power integrity.
Synopsys’ 3DIC Compiler eliminates the need for chip designers to retarget traditional point tools to accommodate multi-die integration or build their own complicated flows by providing a silicon-first approach. 3DIC Compiler users report substantial design productivity benefits for multi-die chips at advanced nodes, with turnaround times reduced from months to hours.
The bottom line: design convergence challenges for multi-die chips requires a different approach to using non-convergent, disjointed point tools and flows. Requirements for signal and power integrity and thermal analysis all increase with these vertically stacked dies, so it’s essential to address the entire system via a single, integrated environment. A unified, silicon-first platform for multi-die system design and integration enables faster convergence with reduced design iterations for 3D-ICs that are becoming increasingly critical in compute-intensive applications like AI and high-performance computing.