From Silicon To Software

 

The Link Between Hyperscale Data Centers and Next-Generation Ethernet Connectivity

Hyperscale data center ethernet

By Manmeet Walia, Sr. Product Marketing Manager, and Priyank Shukla, Staff Product Marketing Manager, Solutions Group

It’s no secret that tech giants are heavily investing in hyperscale data centers. Not only are they putting money toward new facilities, but they are also investing in the technology platforms that are enabling increasingly faster data transport and processing. In fact, the global hyperscale data center market size is expected to grow from $25.08 billion in 2017 to $80.65 billion by 2022, according to optical researchers.

These lightning-fast speeds are enabling technology that is used to predict weather patterns, help autonomous vehicles drive, deliver new artificial intelligence (AI) functionality, and enable the huge amounts of video conferencing taking place as more employees than ever are working from home. It has even played a role in helping researchers develop the COVID-19 vaccine and will continue to power advanced medical research.

But how do hyperscale data centers themselves foster the faster speeds and longer reach required for these emerging technologies?

Read on as we dive into the importance of long-reach connectivity in high-performance computing (HPC) systems-on-chip (SoCs), why it is critical to have working silicon in advanced FinFET processes, and how Synopsys is helping customers in this arena.

Hyperscale Data Centers Propel Next-Generation Ethernet Connectivity

As hyperscale data centers transition to faster, flatter, and more scalable network architectures, the need for higher bandwidth with efficient connectivity in longer distances increases.

Hardware accelerators, AI, and deep learning functions in data centers that power the technology mentioned above (and much more) all consume substantial amounts of bandwidth, forcing high-end data centers to quickly move to next-generation interconnects operating at higher data rates.

Ethernet is the primary interface for outside-the-box connection or box-to-box connections.

As 100Gbps Ethernet matures in hyperscale data centers, the cost-sensitive enterprise data center ecosystem will start taking advantage of the current generation technologies and begin their own transition  to higher rates (see figure below for more on the evolution of Ethernet speeds).

Ethernet speed chart

Rack Switch, Long-Reach Connectivity Use Cases

Network engineers choose interconnects based on application space, length requirements, density, form factor, power consumption, and available products. There are many different factors and variations that can be implemented, but let’s narrow in on a common interconnect: shielded balanced copper cabling for short distances of a few meters (m) targeting box-to-box and intra-rack connections.

These compute units that need to communicate with the top of the rack switch are typically connected with copper cables rather than optics to cut down on costs. A high-performance, long-reach SerDes is needed to ensure error-free links via copper cables for rack switch communication. The next-generation, monolithic 51.2T switch with 100Gbps SerDes will need 512 lanes to be integrated in a single SoC. This not only adds signal and power integrity challenges, but designers need to be able to factor in all of the thermal considerations that go along with such integration.

Enter DesignWare 112G Ethernet PHY IP

Last month, we announced the silicon proof of DesignWare® 112G Ethernet PHY IP in the 5nm FinFET process, delivering significant performance, power, and area advantages. The 112G Ethernet PHY enables true long-reach channels for up to 800G hyperscale data centers, networking, and AI SoCs.

Keeping in mind the Holy Grail of power, performance, and area (PPA), DesignWare 112G Ethernet PHY in 5nm:

  • Enables designers to optimize highly dense SoCs with placement-aware IP that maximizes bandwidth per die-edge through stacking and placement on all four edges of the die
  • Demonstrates zero bit-error rate post forward-error correction in greater than 40dB channels while offering power efficiency of less than five picojoules per bit (pJ/bit)
  • Supports the Pulse-Amplitude Modulation 4-Level (PAM-4), Non-Return-to-Zero (NRZ) signaling, and independent, per-lane data rates for ultimate flexibility to address a broad range of protocols and applications

Since every customer has unique requirements, Synopsys develops IP that is very flexible and can handle supporting different metal stacks, bump structures that necessitate unique placement requirements, and more. When it comes to logical integration of synthesis review, layout review, timing reviews, package design, power network design, etc., we work with you every step of the way with design checklists and reference designs based on past experiences to make sure no mistakes are made along the way.

At the end of the day, designers need reliable interface IP that can support different Ethernet electrical interfaces in a single PHY and is verified and licensed from a single IP vendor, to keep up with the rising data rates and increased bandwidth demand. This combination provides the flexibility, ROI, and short time-to-market windows that are crucial in today’s competitive landscape.

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