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Key Power Predictions for Chip Design in 2021

soc design 2021 predictions

By Godwin Maben, Low Power Architect and Scientist, Digital Design Group

In the world of chip design, power considerations are nothing new. Design engineers are constantly working to optimize for power and performance targets, and “low power” has been a longstanding mantra. But as we consider how applications like high-performance computing (HPC) and artificial intelligence (AI) are driving the need for larger chips, this brings new dynamics to the power equation. In this blog post, we’ll take a look at the key power considerations for chip design that will likely emerge over the course of this year.

Cerebras has been making waves for introducing the Wafer-Scale Engine (WSE), the largest chip ever built. At 46,225mm2 with 1.2 trillion transistors and 400,000 AI-optimized cores, the Cerebras WFE is at the heart of the company’s Cerebras CS-1 deep learning system. If you consider the physics of chips that are beyond 800mm2, you’ll recognize that you won’t get the same benefits in terms of performance unless you carefully manage the power. Because of the increasingly high volume of computing required for AI, the chips will only continue to get bigger with more transistors and, perhaps, go vertical. One of the key limitations in terms of chip performance will be temperature. So many transistors on the same die results in high density, so junction temperature will go up and chip performance, as a result, will start declining. Designers will have to consider thermal runaway, since performance will essentially be limited by power. Indeed, electronic design automation (EDA) vendors are continuing to work on elevating temperature as one of the key targets that chips must address for successful operation (along with the familiar power, performance, and area (PPA)).

One of the advantages of a vertical architecture is that all of the dies do not have to be on the same geometry. As a result, designers can better manage overall power by utilizing the process node best suited for the task at hand for each given die. One of the challenges of 3D-ICs, however, is ensuring that power is delivered through all parts of the device without a loss in voltage. That’s why power integrity and having an efficient power delivery network have become even more critical, particularly for larger chips. Designers strive to deliver voltage from point A to point B with minimal drop. However, at lower geometries, total capacitance increases. With higher gate capacitance comes higher dynamic power, so designers will need to look at, and seek to better monitor, dynamic and static IR drop from a functional perspective.

Speaking of dynamic IR drop, that is another challenge as it is very dependent on the activity. How do you get the right vector that is representative of how it will behave in a real system in the field? This depends on the function being executed. Yet, the quality of the vectors is the most critical component for dynamic power analysis and optimization. Emulation-based power analysis provides a solution. For example, the ZeBu® Server 4, the industry’s fastest emulation system, supports power analysis by pinpointing the right window/vectors while a real application is run on the SoC design representing a real system. The designer can then more accurately determine how much power the SoC will consume and adjust the RTL accordingly.

Managing Power in IoT Designs

While chips for applications like AI are getting bigger, on the other end of the spectrum are battery-powered IoT devices. For these devices, chips are continuing to shrink in size, and low power consumption is essential for longer battery life and better performance. As chips for these applications move to ever-smaller process nodes—think 7nm, 5nm, or 3nm—and to gate all-around architectures, leakage becomes a more critical issue to manage. At lower voltage operation, designers will need to look more carefully at variation across transistors as well as timing.

Clock gating has evolved quite a bit over the years, from simple clock gating to self-gating to sequential clock gating. This has been the most important weapon of choice for reducing power for ages.  While dynamic voltage scaling (DVS) provides a fairly common power-reduction technique, many designs are starting to move to the more advanced adaptive voltage and frequency scaling (AVFS) methodology. In November 2020, Synopsys acquired Moortec, a leading provider of in-chip monitoring technology specializing in process, voltage, and temperature (PVT) sensors. Moortec sensors, a key component of Synopsys’ Silicon Lifecycle Management (SLM) platform, provide in-chip data that enables designers to better control the voltage on their designs’ clock networks. This creates a significant analytics opportunity to assess the make-up of each individual chip and measure dynamic conditions throughout the lifetime of a device, presenting new possibilities for power optimization at both chip and product-wide levels.

Synopsys provides a software-driven low-power platform that spans architecture analysis to block RTL power analysis and SoC power analysis and optimization. The platform includes:

By covering every step of the SoC design flow, this low-power platform enables designers to consider and optimize for power from the very start of their process. As chips become larger for applications like AI and smaller for the IoT, the trends are making it crystal clear that power cannot be an afterthought.

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