Posted by Editorial Team on December 22, 2020
By Editorial Team
As the year comes to a close, it brings with it a natural time for reflection. One thing is certain: no one could have predicted everything that would happen in 2020. While in many ways, it may feel that our individual lives have slowed down as trips and events got canceled and we left our houses a lot less, the world of technology kept on racing ahead to enable the infrastructure that kept us connected.
The era of “Smart Everything,” where devices are getting smarter and connected, and security is an important consideration, was in full force this year. From the chip to the cloud, Synopsys technology is at the heart of innovations that are transforming the way people work and play. New requirements for power, reliability, mobility, real-time connectivity, and security are at the foundation for Smart Everything, and Synopsys was there this year to help innovators continue to advance the technology that impacts all our lives.
Let’s take a look back on all of our 2020 Smart Everything milestones.
Artificial intelligence (AI) continues to transform how we process and experience information ― at work, at play, on the go. It’s easy to see the impact of some AI applications in our everyday lives, like the smart devices in our living rooms. However, there are some applications that we don’t see every day, but are just as important for improving our quality of life.
One such example is our Simpleware™ AS Ortho, a machine learning-based auto segmentation module for 3D image processing that we released a major update for in March. 3D image segmentation of MRI and CT scans is a big, time-intensive challenge for surgical and engineering teams. The machine learning and AI implemented in Simpleware AS Ortho delivers, on average, a 20x to 50x faster segmentation for clinical images with no user time involved, which frees up engineers’ time to devote to high-value tasks.
On the flip side, AI is also being implemented to create the very chip design tools, methodologies, and processes that are needed to enable innovation in the medical field, autonomous vehicles, and more. That’s where our DSO.ai™ technology comes into play, which we announced earlier this year. It stands for “Design Space Optimization AI,” representing one of the most challenging chip design processes in the entire development flow. Specifically, it searches the vast combined space of design and silicon technology choices that human engineers don’t have the time to sort through to identify optimal recipes to balance performance, power, and area (PPA). In fact, lower power design is one of the key challenges for the AI chip (a topic we detailed more in another blog post published in September).
This October, we announced the latest stages in our ongoing collaboration with IBM Research’s AI Hardware Center and our role in IBM’s vision of achieving 1,000x improvement in AI compute performance by 2029. Synopsys’ participation includes both technology and engineering personnel collaborating with the IBM researchers and other partners. Many of our tools are being used to drive progress, and we are contributing in three key areas: silicon engineering, silicon IP, and silicon design & verification. The news reached far and wide, landing in national tech publications such as TechRepublic, The Silicon Review, EE Times, and InsideHPC.
Autonomous driving is another very exciting topic in the Smart Everything era and one that requires increasing amounts of compute power and software content ― and years of development time. We started the year strong by joining the new Autonomous Vehicle Computing Consortium in January. It’s been a privilege to work alongside leading experts in the automotive, automotive supply, semiconductor and computing industries to help develop recommendations for system architectures and computing platforms that will be used to address the challenges of deploying self-driving vehicles at scale. We also launched our new integrated DesignWare™ MIPI C-PHY/D-PHY IP, delivering less than 1.3pJ/bit while operating at 24 Gbps for high-resolution imaging and display SoCs targeting automotive applications.
It’s safe to say that this year the automotive industry continues to experience a major disruption in the development process to accommodate trends such as big data and autonomous everything. That’s why we’ve been leveraging a Triple Shift Left approach to help our customers transform a traditionally linear automotive development process into a parallel one. Triple Shift Left enables design teams to identify problems up to 18 months earlier, before hardware is even available.
Speaking of hardware, the smarter cars of today rely on smarter sensors. Sensors such as radar, LiDAR, image, pressure, and ultrasonic collect data from within and around the vehicle to make important safety decisions. You can learn more about the design challenges that come along with vehicle sensors and what sensors need to be effective in this blog post.
Although mobile carriers started to deploy 5G late last year, 2020 was the year that we really saw widespread adoption of this technology. 5G provides a mobile-first experience with instantaneous data transfer and is serving as the catalyst for mainstream adoption of autonomous vehicles, virtual reality, and smart cities.
5G is driving tremendous increases in connection speed, bandwidth, and data throughput for mobile applications and beyond by introducing carrier aggregation, massive MIMO, and increased throughput with advanced modulation and high-bandwidth channels via mmWave spectrums. These advancements add more challenges around baseband, infrastructure, and application processor technologies, creating demand for new innovative IP.
Synopsys interface, data converter, security, and processor IP help designers build advanced chipsets and a reliable infrastructure for 5G mobile that will meet new and emerging standards for data security. We talked about the biggest 5G chip design challenges and how the industry is ramping up to meet the demand in this blog post.
While high-performance computing (HPC) and the cloud have been hot topics for many years, this year we saw an increased demand for these technologies due to COVID-19. In 2020, there was a massive shift to online services for businesses, entertainment, gaming, and schools due to shelter-in-place orders necessitated by COVID-19. According to estimates from Gartner, 80% of enterprises will move away from their traditional data center by 2025 versus 10% today.
As we continue to witness this shift, the semiconductor market in data centers is expected to reach $177 billion in 2027, while data traffic is projected to be at 330 zettabytes in 2030, according to the 2019 IBS Global Semiconductor Market Report.
Re-architecting the cloud data center to support the latest applications is driving the next generation of semiconductor SoC designs that support new high-speed protocols and optimize data processing, networking, and storage in the cloud. One of these design innovations is die-to-die connectivity for extra-short reach (XSR) and ultra-short reach (USR) links, as well as high-bandwidth interconnect (HBI). Integrating new and complex HPC functionality is pushing die sizes to — and beyond — their manufacturing limits. In addition, while huge monolithic dies offer high performance, they can drive up overall costs. To overcome cost and yield issues, as well as for scalability and flexibility, designers are splitting the system-on-a-chip (SoC) and turning to die-to-die IP for enhanced connectivity.
There are many other ways beyond what we’ve already mentioned where Synopsys is injecting innovation into the chip design process. Chip verification is one of the most critical, challenging, and time-consuming tasks for designers. Done correctly, it’s the key to meeting design schedules and ensuring a better-quality result.
Prototyping is a critical component in the verification continuum and can be done in many different ways. The use of virtual prototyping for the development of semiconductor SoCs is a valuable strategy. In this context, the virtual prototype is used as an alternative to the electronic hardware with the objective to develop the embedded software that will execute on the electronic system and fulfill its expected functions. We’re seeing this methodology being applied in mobile and consumer SoC applications as well as automotive, networking, and wireless modems.
Traditional prototyping, typically called field programmable gate array- (FPGA-) based prototyping, can provide a lot of valuable benefits including highly efficient debug productivity, the highest verification performance, and modularity and scalability. When used in conjunction with virtual prototyping, hybrid methodologies can reduce development time and enhance productivity even further.
In areas such as high-performance computing, data centers, autonomous vehicles, transportation, and industrial IoT, quality, security, and reliability are growing concerns that cost companies billions of dollars to monitor and address. This October, we introduced the industry’s first Silicon Lifecycle Management (SLM) platform, a new holistic concept that closes the silicon loop to optimize all phases of the silicon lifecycle to help these companies. The Synopsys SLM platform enables new levels of insights for both SoC teams and their customers to optimize operational activities at each stage of the device and system lifecycles.
Photonic technologies are enabling innovations in data communications, sensing, and imaging. As demand increases for lightning-fast, energy-efficient communications, integrated photonics provides a key enabling element of the solution. In September, we introduced OptoCompiler, the industry’s first unified electronic and photonic design platform, which combines mature and dedicated photonic technology with Synopsys’ electronic design tools to enable engineers to produce and verify photonic IC designs quickly and accurately. We discussed how Synopsys is transforming photonic IC design in this blog post.
It’s no surprise that software and semiconductors in the satellites, aircraft, and navigation systems that support our national aerospace and defense programs need ironclad security. The increased demand for security has led to the emergence of risk-based DevSecOps, which adds security activities, increases depth, and improves testing governance. By shifting left from a reactive to proactive security approach and applying autonomous testing, developers can incorporate security at the right time and place. It’s clear that security practices need to align with the increased speed in software development by being incorporated across the software development lifecycle (SDLC) from start to finish. According to Gartner, DevSecOps practices will be embedded in 80% of rapid development teams by 2021.
But it’s not just software that needs to be considered. Hardware security is also of increasing importance to defense programs. In June, Defense Advanced Research Projects Agency (DARPA) announced that it had selected Synopsys as a Prime Contractor for the Automatic Implementation of Secure Silicon (AISS) program. Over the next four years, we will work on bringing security to the forefront of the chipset design process that has been previously hyper-focused on performance and cost objectives. Not only that, but the final DesignWare IP and “security-aware” EDA tools developed are expected to accelerate the time-to-market timeline from architecture to security-hardened product from one year to one week.
We know that security is of increasing importance for consumers as well. Synopsys celebrated the 17th annual Cybersecurity Awareness Month in October this year. One of the key takeaways from our celebration was that everyone in our organization needs to be part of the “Human Firewall.” This means being proactive in your personal cybersecurity practices and reporting any activity that seems unusual (i.e., a suspected phishing email). You can read more about the “Human Firewall” and how cybersecurity is driving business forward for Synopsys in this Q&A with CSO Deirdre Hanford.
Despite working from home for the majority of 2020, we still found ways to stay connected to each other. This also applied to our very first class of virtual summer interns. Every Tuesday, interns were given a “challenge” with a fun learning focus, and one of those challenges asked interns to submit personal artwork that represented the Synopsys brand. Check out the creative works of art, including the winning submission by Chaitanya P. that depicted an intern climbing the pyramid of success built on Synopsys’ values in this blog post.
We also continued on our path of sustainability. In June, we announced our commitment to reducing greenhouse gas emissions by 25% by 2024, compared with our 2018 baseline. In addition, Synopsys achieved CarbonNeutral® certification across its global operations for the second consecutive year, offsetting approximately 90,000 metric tons of carbon dioxide equivalent in 2020.
Finally, we still attended, spoke at, and hosted the industry events we all know and love, this time virtually. In case you missed them you can find recaps of our favorite moments from SEMICON West and DAC, ARC Processor Virtual Summit, and the AI Hardware Summit on the blog.
We wish you and your loved ones a happy holiday season!
In the era of Smart Everything—where devices are getting smarter and everything is connected—Synopsys technology is at the heart of innovations that are changing the way we live. Read on to get the latest look at trends in semiconductor chip design, verification, IP integration, and software security and quality. Learn about the ins and outs of electronic design automation from our industry-leading experts and how silicon and software are powering the automotive, artificial intelligence, 5G, cloud and IoT markets.