From Silicon To Software

 

FPGA Prototyping Brings More Performance, Scalability to SoC Hardware and Software Development (Part 3)

fpga prototyping

By Marc Serughetti, Senior Director Product Marketing and Business Development of Embedded Software Solutions, and Johannes Stahl, Senior Director Product Marketing and Business Development for Emulation and Prototyping

In this the third and final post on how prototyping fits into the overall SoC design and verification continuum, we provide an overview of the role and benefits of ‘traditional’ prototyping, typically called Field Programmable Gate Array (FPGA) based prototyping.

As stated in previous posts, prototyping (of various methods) is a valuable element in a software-to-silicon strategy, and can be used effectively beyond the silicon level to platform true system-level design, a topic we will address in future posts. Being able to develop a working prototype in the shortest amount of time and well ahead of working silicon is critical in competitive markets.

FPGA-based prototypes provide design cycle reduction for complex SoC development through:

  • Highly efficient debug productivity
  • The highest verification performance
  • Enabling modularity and scalability

When used in conjunction with virtual prototyping, hybrid methodologies can reduce development time and enhance productivity even further.

As its name implies, FPGA-based prototyping uses actual FPGA-based hardware and associated software tools to assist in the verification process. This consists of a dedicated system that uses one or more high-capacity FPGAs to allow both hardware designers and software programmers to execute designs at high speeds for system validation and software development purposes. As with virtual protypes, FPGA-based prototypes enable software development but differ because they use the actual register-transfer level (RTL) in the design process, making them well-suited to performing concurrent verification of hardware and software well ahead of chip fabrication to avoid costly device re-spins. A primary difference is that while virtual prototyping relies on very efficient transaction level models (TLMs) for pre-RTL level verification, FPGA-based prototyping uses synthesizable RTL to provide cycle-accurate, high-performance execution and real-world interface connectivity.

Fastest Path to a Prototype

FPGA-based prototyping platforms such as the Synopsys HAPS (High-Performance ASIC Prototyping System) solution are aimed at enabling the fastest path to a functioning prototype. They are driven by a suite of integrated tools that provide developers with interactive SoC-level analysis and debug capabilities, as well as insight into the various IP and other elements of a complex SoC, including real world I/O and custom subsystems. They also interface to other necessary tools in the design and development process, including test environments.

Also, as mentioned, FPGA-based prototyping is especially valuable in the software development process, which is increasingly the most time-consuming and complex aspect of SoC design. By using optimized FPGA prototypes, developers have the performance they need to bring up and verify their operating systems far in advance of having access to the actual targeted hardware. Since a prototyping system such as Synopsys’ HAPS platform can achieve internal system frequencies in 100s of megahertz, developers can execute the low-level firmware of the software stack, as well as the full operating system and even applications.

Of course, verification performance is a key benefit of physical prototyping. Using high performance FPGA-based prototypes, developers can achieve speeds that are orders of magnitude faster than other types of verification, such as simulation or emulation. This performance can scale with the complexity of design thanks to the flexibility of prototyping solutions that allow design partitioning across multiple FPGAs to be utilized in order to handle the design size and deliver enhanced verification throughput. This also brings the added benefit of more time to perform exhaustive verification of large designs, or to allow additional ‘what if’ exploration of design options, even on specific portions of the design.

While full-chip verification is the primary objective, physical prototyping supports other use cases, including proof-of-concept research, test pattern generation for DUTs, IP development and even end-user evaluation – all before final working silicon is available. The portability of a modern prototyping solutions means they can be quickly assembled in the field for customer demonstrations, industry conferences, “plug-fests” and validation scenarios outside of the lab environment.

Multi-FPGA Approaches and Partitioning

Because of the size of current generation SoCs, developers often utilize multiple FPGAs in their prototyping methodology to increase throughput and to break the design down into manageable pieces. Such an approach requires automated partitioning tools to help guide the process step-by-step, from importing RTL to the export to the synthesis tool. Synopsys supports its prototyping solution with the ProtoCompiler tool, which accepts multi-million gate ASIC RTL source and synthesizes it directly into multiple FPGAs. As part of the tool’s feature set, constraint-driven partition algorithms generate optimized partitions that span multiple FPGAs to quickly solve the most difficult partition problems while optimizing for the fastest system clock performance.

Hybrid Prototyping Compresses Verification Time Further

As we have seen in our last two posts, prototyping holds much potential to reduce verification time, improve engineering productivity and help meeting demanding product development schedules The entire SoC design and verification flow works best as an integrated flow and that applies within the prototyping environments as well.

Many design teams utilize the benefits of virtual and FPGA-based prototyping in tandem, a hybrid approach that represents the best of both the worlds, drastically reducing the time to design bring-up and re-configuration. In the Synopsys environment, that means combining the flexibility and visibility of our Virtualizer virtual prototypes with the performance and access to the real-world hardware interfaces that FPGA-based prototypes using HAPS enable.

Hybrid prototyping gives design teams a scalable methodology that is effective throughout the verification process. It allows team to easily partition SoC design blocks between virtual and FPGA-based prototyping environments to maximize performance of each particular verification requirement. By combining the two types of prototyping, developers can perform system bring-up by using virtual prototyping for new design blocks and rely on FPGA-based prototyping for existing logic, for example. Using a hybrid approach within the Synopsys environment allows both a connection to real-world I/O model interfaces through analog PHYs or test equipment attached to a HAPS FPGA-based prototype as well as the ultimate flexibility to mix and match model abstractions to leverage legacy RTL with SystemC/TLM models that are faster to implement and available sooner in a project lifecycle.

Prototyping Provides Key Links in the Verification Continuum

These last three posts have shown that prototyping is an important tool in the product development process to significantly reduce verification time. Its ability to enable detailed insights and verification capabilities for targeted hardware well before silicon is available gives systems designers, software developers and SoC hardware engineers a head start on ensuring a functioning chip. Our focus is on providing development teams the fastest and most productivity-oriented path to working protypes with its virtual and FPGA-based platforms. Our prototyping solutions can be applied from individual IP blocks to processor subsystems to complete SoCs to offer extremely high performance throughput, scalability across entire design teams and ecosystems, and productivity-oriented debug – all within the seamless flow of a varication continuum that addresses specific pain point in the SoC flow.

To read Part 1 and Part 2, click on the following links: