Scott and I are out at IDF (Intel Developer Forum – not the Tavor-wielding IDF) this week, where the keynote yesterday was all about Virtual Reality, Augmented Reality, and Merged Reality …. oddly not much was said about plain old real reality. If you missed us last week at Flash Memory Summit (FMS) please stop by Booth #230 and say “Hi”. Heck, even if you didn’t miss us, come by anyway! Speaking of FMS, I should first give you an…. FMS AAR (After Action Report) I apologize for not posting sooner, but after spending so much time last week chanting under my breath my favorite old Polish folk-saying (“Not my circus, not my monkeys!”) I was struggling with exactly what to post about FMS. Suffice it to say that there were a number of logistical “challenges” with the show itself – culminating in a no-show of the moderator for the PCIe/NVMe session. However, I did have a good turnout of 50-60 folks for my session on using PCIe 4.0 in SSDs. I really appreciated everyone’s patience as the speakers worked out our own lineup and introductions (and no, for the record, despite how I introduced him, Debendra didn’t *actually* invent a banana peeler). There was definitely a lot of interest in PCIe 4.0 from SSD folks and that was evident in our booth traffic as well. This shouldn’t be surprising to anyone given new technologies in non-volatile media and the relative ease of aggregating NAND (or other) chips to get extremely high bandwidth, not to mention that most common PCIe SSD form-factors are limited to 4 lanes. (Remember that SFF-8639, now sometimes called U.2, and the newish M.2 form-factor both top out at PCIe x4 configurations so their only real choice for more bandwidth is higher signaling speed.) Regardless of the hiccups, thanks for all those who stopped by – including some old friends and colleagues:
Sorry this is so last-minute, but any of you who are at Flash Memory Summit this week, please stop by Tuesday night for “Beer, Pizza and Chat with the Experts” (7pm-8:30pm) where I’ll have a table on SSD Interfaces. Of course this will be completely neutral 😀
Hopefully all of you have made plans to attend this year’s PCI-SIG Developers Conference (aka Devcon) next week in Santa Clara. This is THE event to learn about PCI Express technology, and network with your fellow PCIe ecosystem members. Of course Synopsys will be there, both on the exhibition hall floor and in the Member Implementation tracks. Come listen to the big dogs from Synopsys R&D teach you (and our competitors) about two important topics. First, come by Track 3 on Tuesday at 3:30pm to hear how we got our DesignWare Root Port IP for PCI Express on the PCI-SIG Integrator’s List as the first *EVER* from an IP provider! Don’t miss the 10:30am Wednesday morning session (also in Track 3) on PCI Express in automotive applications. Yes, it’s true, I’m taking a bit of a rest on this one and “only” presenting PCI-SIG sessions this time, but the other Synopsys presenters will keep you informed, even if they’re not as funny as I think I am 😀
Full disclosure: this is NOT a posting about PCI Express ordering rules, though that’s a great topic which I’ll use for a future posting.
I’ve been thinking for a while (yes, that explains the burning smell) that we should be covering some of the basics of PCI Express here at ExpressYourself in addition to “just” the new stuff. After reading today’s posting, please let me know in the comments whether this is a good idea or not…
“What’s this?!?!? A blog posting from Richard? Wasn’t he killed in a fiery camel-riding crash at the last PCI-SIG Israel event or something?”
The video at ARM TechCon of our 2nd PCIe Gen4 system got kind of lost in our end of the year, Thanksgiving, Christmas, New Years, End of the 1st Quarter rush. I know that my videos of PCIe won’t win any Oscars, but one wonders if someone is just hiding this masterpiece from the public eye. Ok, ok, it’s not a masterpiece, but I’m sure folks would like to see PCIe 4.0 in action. Just for fun, see if you can find my mistakes! There are at least 5!
Ok, Ok, I confess to a bit of a sensationalist streak 🙂 [Who, me??] In truth, the world’s second PCIe Gen4 system is brought to you by the very same people who brought you the world’s first – us, Synopsys that is.
Wow, it’s been QUITE the busy week here! I’m actually out at the PCI-SIG Developers Conference Asia-Pacific Tour 2015 and it’s been very much a whirlwind. It’s been 10 years since the PCI-SIG was in China, and while that trip might have been memorable for my 2.2 seconds of “fame” on Chinese TV, the China event was held in Beijing and not Shanghai, so the PCI-SIG team didn’t have any experience with this venue. That translated to my flying out Sunday morning to get to China Monday night so we’d have Tuesday to prepare for Wednesday’s show. I had a direct flight from LAX to Shanghai’s PVG on Boeing’s 787 Dreamliner. While ExpressYourself readers may recall that I’ve griped about some details on that aircraft (which seem to have been improved by this trip) I will say this – it’s a VERY quiet plane! Landing after 13 1/2 hours or so I realized “Hey, I never put my noise cancelling headphones on!” so here’s an official ExpressYourself attaboy (sorry, no cash value) to the team at Boeing!
Yes, yes, I noticed that it’s not Thursday any more, thus the title change. I feel like the IDF wrapup is somewhat anticlimactic though, so I hope you all weren’t hovering over your keyboards waiting for a grand finale.
I’ve been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec so have definitely lived the evolution of PCI Express and PCI since the very beginning! Over the years I have worked on variations of PCI, eventually moving on to architecting and leading the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. For the last ten plus years I've also had the honor of serving on the PCI-SIG Board of Directors and holding a variety of officer positions. I am still involved in PCI-SIG workgroups and I present at many PCI-SIG events around the world. Back before the dawn of PCI, I received my B.S.E.E. from Rice University, and hold over two dozen U.S. Patents, many of which relate to PCI technology.